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microconverter ? mul t ichannel 24-/16-bit adcs with embedded 62 kb flash and single-cycle mcu aduc845/aduc847/aduc848 rev. b in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2005 analog de vices, i n c. al l r i ght s r e ser v ed . fea t ures high resolution -? ad cs 2 independent 24-bit a d cs on the ad u c845 single 24-bit a d c on the ad u c847 an d single 16 -bit adc on the ad uc848 up t o 10 adc i n put channels on all par t s 24-bit no missi ng c o des 22-bit rms ( 19. 5 bit p - p) ef f e c t iv e resolution o f f s et drif t 10 nv/c, gain dr if t 0.5 p p m/c ch op enabled memor y 62-k b yt e on- c h i p f l ash/ee pr ogr a m memor y 4-k b yt e on- c hi p f l ash/ee da ta memor y f l ash/ee , 100-y ear ret e ntion, 100 k c y c le end u r a nc e 3 le v e ls of f l as h/ee pr ogr a m memor y securi t y in- c ir cuit serial download (no e x t e rnal hardwar e ) high speed use r download (5 s e c) 2304 bytes on- c hip da ta r a m 8051-base d c o re 8051 - c ompa tible instruc t ion s e t high per f ormanc e single - c y cle c o r e 32 kh z e x t e rna l cr y s tal o n - c hip pr ogr a mmable pll (12.58 mhz ma x) 3 16-bit time r/c o un t e r 24 pr ogr a mmable i/o lines , plu s 8 analog or d i gital inpu t lines 11 int e rr upt sourc e s , t w o priorit y le v e ls d u al da ta pointer , e x tende d 1 1 -bit stack poi n ter o n - c hip periph er als in t e rnal pow e r- on r e set cir c ui t 12-bit v o ltage output d a c d u al 16-bit -? d a cs o n - c hip t e mper a t ure sensor ( a d u c8 45 only) dual e x cita tion curr en t sour c e s (200 a ) t i me in t e r v al coun t e r (w ak e - up/rt c timer) u a rt , spi?, an d i 2 c? seria l i/o high speed de dic a t e d bau d ra t e gener a t o r ( i ncl . 115,200) w a t c hdog timer ( w d t ) p o w e r sup p ly monit o r (psm) po w e r normal: 4.8 m a ma x @ 3. 6 v ( c ore clk = 1.5 7 mhz) p o w e r- down: 20 a ma x with w a k e -up timer running specified f o r 3 v and 5 v o p era t io n p a ck age and t e mper a t ur e r a nge: 52-lea d mqfp ( 14 mm 14 m m ), ?40 c t o +1 25c 56-lea d lfcsp (8 mm 8 mm) , ?40 c t o +85 c applic a t io ns multichannel s e nsor monit o ri ng industrial/en v i r onmen t al instrumen t a t ion w e igh sc ales , p r essur e sensors , t e mper a t ur e monit o ring p o r t able instrumen t a t ion, ba tt er y - pow e r e d sy st ems da ta logging , pr ecision sy st em monit o ring func ti on a l bl ock di a g r a m 62 k b ytes flash/ee program memory 4 k bytes flash/ee data memory 2304 bytes user ram 3 16 bit timers ba ud r a t e t i m e r 4 parallel ports single-cycle 8061-based mcu aduc845 temp sensor current source ain1 ain10 aincom reset dv dd dgnd wake-up/ rtc timer iexc1 iexc2 pwm0 pga buf mux auxiliary 24-bit - ? adc primary 24-bit - ? adc dac buf pwm1 12-bit dac av dd dual 16-bit - ? dac dual 16-bit pwm power supply mon watchdog timer ua rt, spi , a n d i 2 c serial i/o mux 04741- 001 xtal2 xtal1 osc avco agnd pll and prg clock div por refin+ refin? refin2? refin2+ external v ref detect internal band gap v ref f i g u re 1. a d uc8 4 5 f u nc t i on al bl ock d i ag r a m
aduc845/aduc847/aduc848 rev. b | page 2 of 108 table of contents specifications ..................................................................................... 4 abosolute maximum ratings ....................................................... 10 esd caution ................................................................................ 10 pin configurations and function descriptions ......................... 11 general description ....................................................................... 15 8052 instruction set ................................................................... 18 timer operation ......................................................................... 18 ale ............................................................................................... 18 external memory access ........................................................... 18 complete sfr map .................................................................... 19 functional description .................................................................. 20 8051 instruction set ................................................................... 20 memory organization ............................................................... 22 special function registers (sfrs) ............................................ 24 adc circuit information .......................................................... 26 auxiliary adc (aduc845 only) ............................................ 32 reference inputs ......................................................................... 32 burnout current sources .......................................................... 32 reference detect circuit ........................................................... 33 sinc filter register (sf) ............................................................. 33 - ? modulator ............................................................................ 33 digital filter ................................................................................ 33 adc chopping ........................................................................... 34 calibration ................................................................................... 34 programmable gain amplifier ................................................. 35 bipolar/unipolar configuration .............................................. 35 data output coding .................................................................. 36 excitation currents .................................................................... 36 adc power-on .......................................................................... 36 typical performance characteristics ........................................... 37 functional description .................................................................. 39 adc sfr interface ..................................................................... 39 adcstat (adc status register) ........................................... 40 adcmode (adc mode register) ......................................... 41 adc0con1 (primary adc control register) ..................... 43 adc0con2 (primary adc channel select register) ........ 44 adc1con (auxiliary adc control register) (aduc845 only) ............................................................................................ 45 sf (adc sinc filter control register) .................................... 46 icon (excitation current sources control register) .......... 47 nonvolatile flash/ee memory overview ............................... 48 flash/ee program memory ...................................................... 49 user download mode (uload) ............................................. 50 using flash/ee data memory .................................................. 51 flash/ee memory timing ........................................................ 52 dac circuit information .......................................................... 53 pulse-width modulator (pwm) .............................................. 55 on-chip pll (pllcon) .......................................................... 60 i 2 c serial interface ..................................................................... 61 spi serial interface ..................................................................... 64 using the spi interface .............................................................. 66 dual data pointers ..................................................................... 67 power supply monitor ............................................................... 68 watchdo g ti me r ......................................................................... 69 time interval counter (tic) .................................................... 70 8052-compatible on-chip peripherals .................................. 73 timers/counters ........................................................................ 75 uart serial interface ................................................................ 80 interrupt system ......................................................................... 85 interrupt priority ........................................................................ 86 interrupt vectors ........................................................................ 86 hardware design considerations ................................................ 87 external memory interface ....................................................... 87
aduc845/aduc847/aduc848 rev. b | page 3 of 108 power supplies .............................................................................87 power-on reset operation ........................................................88 power consumption ...................................................................88 power-saving modes ..................................................................88 grounding and board layout recommendations .................89 other hardware considerations ...............................................90 quickstart development system ..................................................94 quickstart-plus development system ..................................94 timing specifications .....................................................................95 outline dimensions ......................................................................104 ordering guide .........................................................................105 revision history 2/05rev. a to rev. b changes to figure 1...........................................................................1 changes to the burnout current sources section ......................32 changes to the excitation currents section................................36 changes to table 30 ........................................................................47 changes to the flash/ee memory on the aduc845, aduc847, aduc848 section......................................................................48 changes to figure 39 ......................................................................57 changes to on-chip pll (pllcon) section ............................60 added 3 v part section heading ..................................................88 added 5 v part section ..................................................................88 changes to figure 70 ......................................................................91 changes to figure 71 ......................................................................93 6/04rev. 0 to rev. a changes to figure 5.........................................................................17 changes to figure 6.........................................................................18 changes to figure 7.........................................................................19 changes to table 5 ..........................................................................24 changes to table 24 ........................................................................41 changes to table 25 ........................................................................43 changes to table 26 ........................................................................44 changes to table 27 ........................................................................45 changes to user download mode section..................................50 added figure 51 and renumbered subsequent figures............50 edits to the dach/dacl data registers section .....................53 changes to table 34 ........................................................................56 added spidat: spi data register section .................................65 changes to table 42 ........................................................................67 changes to table 43 ........................................................................68 changes to table 44 ........................................................................69 changes to table 45 ........................................................................71 changes to table 50 ........................................................................75 changes to timer/counter 0 and 1 data registers section......76 changes to table 54 ........................................................................80 added the sbufuart serial port data register section.....80 addition to the timer 3 generated baud rates section ...........83 added table 57 and renumbered subsequent tables ...............84 changes to table 61 ........................................................................86 4/04revision 0: initial version
aduc845/aduc847/aduc848 rev. b | page 4 of 108 specifications 1 av dd = 2.7 v to 3.6 v or 4.75 v to 5.25 v, dv dd = 2.7 v to 3.6 v or 4.75 v to 5.25 v, refin(+) = 2.5 v, refin(C) = agnd; agnd = dgnd = 0 v; xtal1/xtal2 = 32.768 khz crystal; all specifications t min to t max , unless otherwise noted. input buffer on for primary adc, unless otherwise noted. core speed = 1.57 mhz (default cd = 3), unless otherwise noted. table 1. parameter min typ max unit conditions primary adc conversion rate 5.4 105 hz chop on (adcmode.3 = 0) 16.06 1365 hz chop off (adcmode.3 = 1) no missing codes 2 24 bits 26.7 hz update rate with chop enabled 24 bits 80.3 hz update rate with chop disabled resolution (aduc845/aduc847) see table 11 and table 15 resolution (aduc848) see table 13 and table 17 output noise (aduc845/aduc847) see table 10 and table 14 v (rms) output noise varies with selected update rates, gain range, and chop status. output noise (aduc848) see table 12 and table 16 v (rms) output noise varies with selected update rates, gain range, and chop status. integral nonlinearity 15 ppm of fsr 1 lsb 16 offset error 3 3 v chop on chop off, offset error is in the order of the noise for the programmed gain and update rate following a calibration. offset error drift vs. temperature 2 10 nv/c chop on (adcmode.3 = 0) 200 nv/c chop off (adcmode.3 = 1) full-scale error 4 aduc845/aduc847 10 v 20 mv to 2.56 v aduc848 10 v 20 mv to 640 mv 0.5 lsb 16 1.28 v to 2.56 v gain error drift vs. temperature 4 0.5 ppm/c power supply rejection 80 db ain = 1 v, 2.56 v, chop enabled 113 db ain = 7.8 mv, 20 mv, chop enabled 80 db ain = 1 v, 2.56 v, chop disabled 2 primary adc analog inputs differential input voltage ranges , 5 6 gain = 1 to 128 bipolar mode (adc0con1.5 = 0) 1.024 v ref /gain v v ref = refin(+) ? refin(?) or refin2(+) ? refin2(?) (or int 1.25 v ref ) unipolar mode (adc0con1.5 = 1) 0 C 1.024 v ref /gain v v ref = refin(+) ? refin(?) or refin2(+) ? refin2(?) (or int 1.25 v ref ) adc range matching 2 v ain = 18 mv, chop enabled common-mode rejection dc chop enabled, chop disabled on ain 95 db ain = 7.8 mv, range = 20 mv 113 db ain = 1 v, range = 2.56 v common-mode rejection 50 hz/60 hz 2 50 hz/60 hz 1 hz, 16.6 hz and 50 hz update rate, chop enabled, rej60 enabled on ain 95 db ain = 7.8 mv, range = 20 mv 90 db ain = 1 v, range = 2.56 v footnotes at end of table.
aduc845/aduc847/aduc848 rev. b | page 5 of 108 parameter min typ max unit conditions normal mode rejection 50 hz/60 hz 2 on ain 75 db 50 hz/60 hz 1 hz, 16.6 hz fadc, sf = 52h, chop on, rej60 on 100 db 50 hz 1 hz, 16.6 hz fadc, sf = 52h, chop on 67 db 50 hz/60 hz 1 hz, 50 hz fadc, sf = 52h, chop off, rej60 on 100 db 50 hz 1 hz, 50 hz fadc, sf = 52h, chop off analog input current 2 1 na t max = 85c, buffer on 5 na t max = 125c, buffer on analog input current drift 5 pa/c t max = 85c, buffer on 15 pa/c t max = 125c, buffer on average input current 125 na/v 2.56 v range, buffer bypassed average input current drift 2 pa/v/c buffer bypassed absolute ain voltage limits 2 a gnd + 0.1 av dd ? 0.1 v ain1ain10 and aincom with buffer enabled absolute ain voltage limits 2 a gnd ? 0.03 av dd + 0.03 v ain1ain10 and aincom with buffer bypassed external reference inputs refin(+) to refin(C) voltage 2.5 v refin refers to both refin and refin2 refin(+) to refin(C) range 2 1 av dd v refin refers to both refin and refin2 average reference input current 1 a/v both adcs enabled average reference input current drift 0.1 na/v/c noxref trigger voltage 0.3 0.65 v noxref (adcstat.4) bit active if v ref > 0.3 v, and inactive if v ref > 0.65 v common-mode rejection dc rejection 125 db ain = 1 v, range = 2.56 v 50 hz/60 hz rejection 2 90 db 50 hz/60 hz 1 hz, ain = 1 v, range = 2.56 v, sf = 82 normal mode rejection 50 hz/60 hz 2 75 db 50 hz/60 hz 1 hz, ain = 1 v, range = 2.56 v, sf = 52h, chop on, rej60 on 100 db 50 hz 1 hz, ain = 1 v, range = 2.56 v, sf = 52h, chop on 67 db 50 hz/60 hz 1 hz, ain = 1 v, range = 2.56 v, sf = 52h, chop off, rej60 on 100 db 50 hz 1 hz, ain = 1 v, range = 2.56 v, sf = 52h, chop off auxiliary adc (aduc845 only) conversion rate 5.4 105 hz chop on 16.06 1365 hz chop off no missing codes 2 24 bits 26.7 hz update rate, chop enabled 24 bits 80.3 hz update rate, chop disabled resolution see table 19 and table 21 output noise see table 18 and table 20 output no ise varies with selected update rates. integral nonlinearity 15 ppm of fsr 1 lsb 16 offset error 3 3 v chop on 0.25 lsb 16 chop off offset error drift 2 10 nv/c chop on 200 nv/c chop off full-scale error 4 0.5 lsb 16 gain error drift 4 0.5 ppm/c power supply rejection 80 db ain = 1 v, range = 2.56 v, chop enabled 80 db ain = 1 v, range = 2.56 v, chop disabled footnotes at end of table.
aduc845/aduc847/aduc848 rev. b | page 6 of 108 parameter min typ max unit conditions auxiliary adc analog inputs (aduc845 only) differential input voltage ranges 5, 6 bipolar mode (adc1con.5 = 0) v ref v refin = refin(+) ? refin(?) (or int 1.25 v ref ) unipolar mode (adc1con.5 = 1) 0 C v ref v refin = refin(+) ? refin(?) (or int 1.25 v ref ) average analog input current 125 na/v analog input current drift 2 pa/v/c absolute ain/aincom voltage limits 2, 7 a gnd ? 0.03 av dd + 0.03 v normal mode rejection 50 hz/60 hz 2 on ain and refin 75 db 50 hz/60 hz 1 hz, 16.6 hz fadc, sf = 52h, chop on, rej60 on 100 db 50 hz 1 hz, 16.6 hz fadc, sf = 52h, chop on 67 db 50 hz/60 hz 1 hz, 50 hz fadc, sf = 52h, chop off, rej60 on 100 db 50 hz 1 hz, 50 hz fadc, sf = 52h, chop off adc system calibration full-scale calibration limit +1.05 fs v zero-scale calibration limit ?1.05 fs v input span 0.8 fs 2.1 fs v dac voltage range 0 C v ref v daccon.2 = 0 0 C av dd v daccon.2 = 1 resistive load 10 k? from dac output to agnd capactive load 100 pf from dac output to agnd output impedance 0.5 ? i sink 50 a dc specifications 8 resolution 12 bits relative accuracy 3 lsb differential nonlinearity ?1 lsb guaranteed 12-bit monotonic offset error 50 mv gain error 1 % av dd range 1 % v ref range ac specifications 2, 8 voltage output settling time 15 s se ttling time to 1 lsb of final value digital-to-analog glitch energy 10 nvs 1 lsb change at major carry internal reference adc reference chop enabled reference voltage 1.25 ? 1% 1.25 1.25 + 1% v initial tolerance @ 25c, v dd = 5 v power supply rejection 45 db reference tempco 100 ppm/c dac reference reference voltage 2.5 C 1% 2.5 2.5 + 1% 1% v initial tolerance @ 25c, v dd = 5 v power supply rejection 50 db reference tempco 100 ppm/c temperature sensor (aduc845 only) accuracy 2 c thermal impedance 90 c/w mqfp 52 c/w lfcsp footnotes at end of table.
aduc845/aduc847/aduc848 rev. b | page 7 of 108 parameter min typ max unit conditions transducer burnout current sources ain+ current ?100 na ain+ is the selected positive input (ain4 or ain6 only) to the primary adc ain? current 100 na ain? is the selected negative input (ain5 or ain7 only) to the primary adc initial tolerance at 25c 10 % drift 0.03 %/c excitation current sources output current 200 a available from each current source initial tolerance at 25c 10 % drift 200 ppm/c initial current matching at 25c 1 % matching between both current sources drift matching 20 ppm/c line regulation (av dd ) 1 a/v av dd = 5 v 5% load regulation 0.1 a/v output compliance 2 agnd av dd ? 0.6 v power supply monitor (psm) av dd trip point selection range 2.63 4.63 v four trip points selectable in this range av dd trip point accuracy 3.0 % t max = 85c 4.0 % t max = 125c dv dd trip point selection range 2.63 4.63 v four trip points selectable in this range dv dd trip point accuracy 3.0 % t max = 85c 4.0 % t max = 125c crystal oscillator (xtal1 and xtal2) logic inputs, xtal1 only 2 v inl , input low voltage 0.8 v dv dd = 5 v 0.4 v dv dd = 3 v v inh , input low voltage 3.5 v dv dd = 5 v 2.5 v dv dd = 3 v xtal1 input capacitance 18 pf xtal2 output capacitance 18 pf logic inputs all inputs except sclock, reset, and xtal1 2 v inl , input low voltage 0.8 v dv dd = 5 v 0.4 v dv dd = 3 v v inh , input low voltage 2.0 v sclock and reset only (schmidt triggered inputs) 2 v t+ 1.3 3.0 v dv dd = 5 v 0.95 2.5 v dv dd = 3 v v t? 0.8 1.4 v dv dd = 5 v 0.4 1.1 v dv dd = 3 v v t+ ? v t? 0.3 0.85 v dv dd = 5 v or 3 v input currents port 0, p1.0 to p1.7, ea 10 a v in = 0 v or v dd reset 10 a v in = 0 v, dv dd = 5 v 35 105 a v in = dv dd , dv dd = 5 v, internal pull-down port 2, port 3 10 a v in = dv dd , dv dd = 5 v ?180 ?660 a v in = 2 v, dv dd = 5 v ?20 ?75 a v in = 0.45 v, dv dd = 5 v input capacitance 10 pf all digital inputs
aduc845/aduc847/aduc848 rev. b | page 8 of 108 parameter min typ max unit conditions logic outputs (all digital outputs except xtal2) v oh , output high voltage 2 2.4 v dv dd = 5 v, i source = 80 a 2.4 v dv dd = 3 v, i source = 20 a v ol , output low voltage 0.4 v i sink = 8 ma, sclock, sdata 0.4 v i sink = 1.6 ma on p0, p1, p2 floating state leakage current 2 10 a floating state output capacitance 10 pf start-up time at power-on 600 ms after ext reset in normal mode 3 ms after wdt reset in normal mode 2 ms controlled via wdcon sfr from power-down mode oscillator running pllcon.7 = 0 wake-up with int0 interrupt 20 s wake-up with spi interrupt 20 s wake-up with tic interrupt 20 s oscillator powered down pllcon.7 = 1 wake-up with int0 interrupt 30 s wake-up with spi interrupt 30 s flash/ee memory reliability characteristics endurance 9 100,000 cycles data retention 10 100 years power requirements power supply voltages av dd 3 v nominal 2.7 3.6 v av dd 5 v nominal 4.75 5.25 v dv dd 3 v nominal 2.7 3.6 v dv dd 5 v nominal 4.75 5.25 v 5 v power consumption 4.75 v < dv dd < 5.25 v, av dd = 5.25 v normal mode 11 , 12 dv dd current 10 ma core clock = 1.57 mhz 25 31 ma core clock = 12.58 mhz av dd current 180 a power-down mode 11, 12 dv dd current 40 53 a t max = 85c; osc on; tic on 50 a t max = 125c; osc on; tic on 20 33 a t max = 85c; osc off 30 a t max = 125c; osc off av dd current 1 a t max = 85c; osc on or off 3 a t max = 125c; osc on or off typical additional peripheral currents (ai dd and di dd ) 5 v v dd , cd = 3 primary adc 1 ma auxiliary adc (aduc845 only) 0.5 ma power supply monitor 30 a dac 60 a dach/l = 000h dual excitation current sources 200 a 200 a each. can be combined to give 400 a on a single output. ale off ?20 a pcon.4 = 1 (see table 6) wdt 10 a footnotes at end of table.
aduc845/aduc847/aduc848 rev. b | page 9 of 108 parameter min typ max unit conditions pwm ?fxtal 3 a ?fvco 0.5 ma tic 1 a 3 v power consumption 2.7 v < dv dd < 3.6 v, av dd = 3.6 v normal mode 11, 12 dv dd current 4.8 ma core clock = 1.57 mhz 9 11 ma core clock = 6.29 mhz (cd = 1) av dd current 180 a adc not enabled power-down mode 11, 12 dv dd current 20 26 a t max = 85c; osc on; tic on 29 a t max = 125c; osc on; tic on 14 20 a t max = 85c; osc off 21 a t max = 125c; osc off av dd current 1 a t max = 85c; osc on or off 3 a t max = 125c; osc on or off 1 temperature range is for aduc845bs; for the aduc847bs and aduc848bs (mqfp package), the ra nge is C40c to +125c. 2 these numbers are not production tested but are guaranteed by design and/or characterization data on production release. 3 system zero-scale calibration can remove this error. 4 gain error drift is a span drift. to calculate full-scale error drift, add the offset error drift to the gain error drift time s the full-scale input. 5 in general terms, the bipolar input voltage range to the primary adc is given by the adc range = (v ref 2 rn )/1.25, where: v ref = refin(+) to refin(C) voltage and v ref = 1.25 v when internal adc v ref is selected. rn = decimal equivalent of rn2, rn1, rn0. for example, if v ref = 2.5 v and rn2, rn1, rn0 = 1, 1, 0, respectively, then the adc range = 1.28 v. in unipolar mode, the effective range is 0 v to 1.28 v in this example. 6 1.25 v is used as the reference voltage to the adc when internal v ref is selected via xref0/xref1 or axref bits in adc0con2 and adc1con, respectively. (axref is available only on the aduc845.) 7 in bipolar mode, the auxiliary adc can be driven only to a minimum of agnd C 30 mv as indicated by the auxiliary adc absolute ain voltage limits. the bipolar range is still Cv ref to +v ref . 8 dac linearity and ac specifications are calculated using a reduced code range of 48 to 4095, 0 v to v ref , reduced code range of 100 to 3950, 0 v to v dd . 9 endurance is qualified to 100 kcycle per jedec std. 22 method a 117 and measured at C40c, +25c, +85c, and +125c. typical en durance at 25c is 700 kcycles. 10 retention lifetime equivalent at junction temperature (t j ) = 55c per jedec std. 22, method a117. retention lifetime based on an activation energy of 0.6 ev derates with junction temperature. 11 power supply current consumption is measured in normal mode following the power-on sequence, and in power-down modes under the following conditions: normal mode: reset = 0.4 v, digital i/o pins = open circuit, core clk changed via cd bits in pllcon, core executing internal so ftware loop. power-down mode: reset = 0.4 v, all p0 pins and p1.2 to p1.7 pins = 0.4 v. all other digital i/o pins are open circuit, core cl k changed via cd bits in pllcon, pcon.1 = 1, core execution suspended in power-down mode, osc turned on or off via osc_pd bit (pllcon.7) in pllcon sfr. 12 dv dd power supply current increases typically by 3 ma (3 v operation) and 10 ma (5 v operation) duri ng a flash/ee memory program or erase cycle. temperature range for aduc845bcp, aduc847bcp, and aduc848bcp (lfcsp package) is C40c to +85c. general notes about specifications ? dac gain error is a measure of the span error of the dac. ? the aduc845bcp, aduc847bcp, and aduc848bcp (lfcsp package) have been qualified and tested with the base of the lfcsp package floating. the base of the lfcsp package should be soldered to the board, but left floating electrically, to ensure good mechanical stability. ? flash/ee memory reliability characteristics apply to both the flash/ee program memory and flash/ee data memory.
aduc845/aduc847/aduc848 rev. b | page 10 of 108 abosolute maximum ra tings t a = 2 5 c , u n l e ss ot he r w i s e no t e d. t a bl e 2. p a r a me t e r r a t i n g av dd t o a g nd C0.3 v t o +7 v av dd to dgnd C0.3 v to +7 v dv dd to dgnd C0.3 v to +7 v dv dd to dgnd C0.3 v to +7 v a g nd t o dg nd 1 C0.3 v to +0.3 v av dd to dv dd C2 v t o +5 v analog i n put v o ltage to a g nd 2 C0.3 v to a v dd + 0.3 v r e f e r e nc e i n put v o ltage to a g nd C0.3 v to a v dd + 0.3 v ain/refin c u rr en t (i ndefinit e) 30 ma dig i tal i n put v o l t age to dgnd C0.3 v to d v dd + 0.3 v dig i tal o utput v o ltage t o dgnd C0.3 v t o d v dd + 0.3 v o p era t ing t e mper a tur e r a nge C40c to +125c stor age t e mpera tur e r a nge C65c to +150c junc tion t e mpe r a tur e 150c ja t h ermal i m pedanc e (mqfp) 90c/ w ja ther mal i m pedanc e (lfcsp) 52c/w l e ad t e mper a tur e , s o lder ing v a por p h ase (60 sec) 215c i n fr ar ed (15 sec) 220c s t r e s s es a b o v e t h os e list e d u nde r a b s o l u te m a xim u m r a t i n g s ma y ca us e p e r m a n e n t dama ge to t h e de vi ce. t h is is a st r e ss r a t i ng on ly ; f u n c t i on a l op e r at i o n of t h e d e v i c e a t t h e s e or an y o t h e r con d i t ions a b o v e t h os e list e d i n t h e op era t io nal s e c t ion s o f t h is sp e c if ic a t io n is n o t i m pli e d . e x p o sur e t o a b s o l u t e max i m u m r a t i ng co ndi t i on s fo r ex tende d p e r i o d s ma y a f fe c t de vice rel i a b i l i t y . ________________________ 1 a g nd and dgnd ar e shor t e d in t e r n ally on the adu c 845, aduc847, and aduc848. 2 appli e s t o t h e p1. 0 t o p1.7 pi n s oper a t i n g i n a n a l og or di g i t a l i n put m o des . esd c a ution esd (elec t r o sta t i c dischar g e) sensitiv e devic e . ele c tr os ta tic char g e s as high as 4000 v r e adily ac cumula te on the human body and t e st eq uipmen t and can dischar g e wi thout det e c t ion. although this pr odu c t f e a tur es pr o p r i etar y esd pr otec tio n cir c u i tr y , per m anen t damage ma y oc cur on devic e s subjec ted to high ener gy elec tr o s ta tic dischar g es . ther ef o r e , p r ope r esd pr ecaution s ar e r e c o mmended to a v oid per f or m a nc e degrada t ion or l o ss of func tiona l it y .
aduc845/aduc847/aduc848 rev. b | page 11 of 108 pin conf igura t ions and f u ncti on descriptions 5 2 51 50 49 48 43 42 41 40 47 4 6 4 5 44 1 4 15 16 17 18 1 9 20 21 2 2 23 24 25 26 1 2 3 4 5 6 7 8 9 10 11 13 12 pin 1 identifier to p v i e w (n o t to sc a l e ) 39 38 37 36 35 34 33 32 31 30 29 28 27 p0.7/ad 7 p0.6/ad 6 p0.5/ad 5 p0.4/ad 4 p0.1/ad1 dv dd dgnd p0.3/ad 3 p0.2/ad 2 p0.0/ad 0 ale psen ea p1.1/ain2 p1.2/ain3/refin2+ p1.3/ain4/refin2 ? agnd av dd agnd refin ? refin+ p1.4/ain5 p1.5/ain6 p1.6/ain7/iexc1 p1.7/ain8/iexc2 aincom/dac dac ain9 ain10 reset p3 .0 /rx d p3 .1 /tx d p3 .2 /int0 p3 .3 /int1 dv dd dgnd p3 .4 /t0 p3 .5 /t1 p3 .6 /w r p3 .7 /rd sclk ( i 2 c) p2.7/pwmclk p2.6/pwm1 p2.5/pwm0 p2.4/t2ex dgnd dgnd dv dd xtal1 p2.3/ss/t2 p2.2/miso p2.1/mosi p2.0/sclock (spi) sdata p1 .0 /ain1 p0 .7 /ad7 p0 .6 /ad6 p0 .5 /ad5 p0 .4 /ad4 dv dd dgnd p0 .3 /ad3 p0 .2 /ad2 p0 .1 /ad1 p0 .0 /ad0 ale psen ea 14 1 2 3 4 5 6 7 8 9 10 11 13 12 15 16 17 18 19 20 21 22 23 24 25 26 27 28 42 41 40 39 38 37 36 35 34 33 32 31 30 29 43 45 46 47 48 49 50 51 52 53 54 55 56 pin 1 identifier 44 xtal2 to p v i e w ( n o t t o s cal e) 04741-003 aduc845/aduc847/aduc848 dac reset p3.0/rxd p3.1/txd p3.2/int0 p3.3/int1 dv dd p3.4/t0 p3.5/t1 p3.6/w r p3.7/rd sclock (i 2 c) p1.0/ain1 p1.1/ain2 p1.2/ain3/refin2+ p1.3/ain4/refin2 ? av dd ag nd refin? refin+ p 1 .4/ain 5 p 1 .5 /a in 6 p1.6/ain7/iexc1 p1.7/ain8/iexc2 aincom/dac p2.7/pwmclk p2.6/pwm1 p2.5/pwm0 p2.4/t2ex dgnd dv dd xtal2 xtal1 p2.3/ss/t2 p2.2/miso p2.1/mosi p2.0/sclock (spi) sd a t a dgnd 04741- 002 aduc845/aduc847/aduc848 f i g u re 2. 52-l e ad m qfp pin conf ig u r at io n f i g u re 3. 56-l e ad l f csp p i n conf ig ur a t ion t a bl e 3. p i n f u i n no : p i n no: 56- ty p e 1 description nc ti o n des c ripti o ns p 52-mqfp lfcsp mn e m on i c 1 56 p 1 . 0 / a i n 1 i b a i n 1 c a n b e u y p o w e r - on default, p1.0/ain1 is c o nfigur ed as the ain1 analog input. s e d a s a p s e u d o d i f f er en ti al input when used with ainc om or as the positiv e input of a fully diff e r en tial pair when used with ain 2 . p1.0 has no dig i tal output d r iv er . i t can func tion as a dig i tal inpu t f o r which 0 must be wr itten to the por t bit. as a digi tal input, this pin must be dr iv en high or lo w e x ter n all y . 2 1 p1.1/ain2 i 3 2 p1.2/ain3/refi n2+ i on pow er - o n default, p1.1/ain2 is c o nfigur ed as the ain2 analog input. a i n 2 c a n b e u s e d a s a p s e u d o d i f f er en ti al input when used with ainc om or as the nega tiv e input of a fully diff e r en tial pair when used with ain 1 . p1.1 has no dig i tal output d r iv er . i t can func tion as a dig i tal inpu t f o r which 0 must be wr itten to the por t bit. as a digi tal input, this pin must be dr iv en high or lo w e x ter n all y . 4 3 p1.3/ain4/refi n2? i on pow er - o n default, p1.2/a in3 is c o nfigur ed as the ain3 analog input. a i n 3 c a n b e u s e d a s a p s e u d o d i f f er en ti al input when used with ainc om or as the positiv e input of a fully diff e r en tial pair when used with ain 4 . p1.2 has no dig i tal output d r iv er . i t can func tion as a dig i tal inpu t f o r which 0 must be wr itten to the por t bit. as a digi tal input, this pin must be dr iv en high or lo w e x ter n all y . this pin also f u nc tions as a se c o nd ex ter n al d i ff er en tia l r e f e r e nc e in put, positi v e ter mina l . on pow er - o n default, p1.3/a in4 is c o nfigur ed as the ain4 analog input. ain4 can be used as a pseudo diff e r en ti al input when used with ainc om or as the nega tiv e input of a fully diff e r en tial pair when used with ain 3 . p1.3 has no dig i tal output d r iv er . i t can func tion as a dig i tal inpu t f o r which 0 must be wr itten to the por t bit. as a digi tal input, this pin must be dr iv en high or lo w e x ter n all y . this pin also f u nc tions as a se c o nd ex ter n al d i ff er en tia l r e f e r e nc e input, nega tiv e t e rminal . 5 4 a v dd s a n a l o g supply v o ltage . 6 5 a g nd s analog gr ound . - - - 6 a g nd s a sec o nd analog g r o u n d i s p r o v ided with the lf csp v e rsion only . 7 7 r e f i n ? r e f e r e nc e i n put, nega tiv e t e rminal . i ex t e r n a l diff er en tial 8 8 r e f i n + i ex t e rnal diff er en tial r e f e r e nc e i n put, p o sitiv e t e rminal . f oot n o t e s a t en d of t a ble .
aduc845/aduc847/aduc848 rev. b | page 12 of 108 pin no: 52-mqfp pin no: 56- lfcsp mnemonic type 1 description 9 9 p1.4/ain 5 analog input. ed with aincom or as the positive input of a fully differen tial pair when used with ain6. h 0 i on power-on default, p1.4/ain5 is configured as the ain5 ain5 can be used as a pseudo differenti al input when us p1.0 has no digital output driver. it can function as a digital input for whic must be written to the port bit. as a digi tal input, this pin must be driven high or low externally. 10 10 p1.5/ain6 i of a fully differen tial pair when used with ain5. h 0 on power-on default, p1.5/ain6 is configured as the ain6 analog input. ain6 can be used as a pseudo differenti al input when used with aincom or as the negative input p1.1 has no digital output driver. it can function as a digital input for whic must be written to the port bit. as a digi tal input, this pin must be driven high or low externally. 11 11 p1.6/ain7/iexc1 i/o of a fully differential pair when used with ain8. one or both on power-on default, p1.6/a in7 is configured as the ain7 analog input. ain7 can be used as a pseudo differenti al input when used with aincom or as the positive input current sources can also be configured at this pin. p1.6 has no digital output driver. it can, however, function as a digital input for which 0 must be written to the port bit. as a digital input, this pin must be driven high or low externally. 12 12 p1.7/ain8/iexc2 i/o as ferenti al pair when used with ain7. one or on power-on default, p1.7/a in8 is configured as the ain8 analog input. ain8 can be used as a pseudo differenti al input when used with aincom or the negative input of a fully dif both current sources can also be configured at this pin. p1.7 has no digital output driver. it can, however, function as a digital input for which 0 must be written to the port bit. as a digital input, this pin must be driven high or low externally. 13 13 aincom/dac i/o all analog inputs can be referred to this pin, provided that a relevant pseudo differential input mode is selected. this pin also functions as an alternative pin out for the dac. 14 14 dac o the voltage output from the dac, if enabled, appears at this pin. ---- 15 ain9 i positive input of a fu lly differential pair when used with ain9 can be used as a pseudo differ ential analog inp ut when used with aincom or as the ain10 (lfcsp version only). ---- 16 ain10 i ain10 can be used as a pseudo differ ential analog input when used with aincom or as the negative input of a fu lly differential pair when used with ain9 (lfcsp version only). 15 17 reset i reset input. a high level on this pin for 16 core clock cycles while the oscillator is running resets the device. this pin has an internal weak pull-dow and a schmitt trigger input stage. n 16C 22C25 19 21 .7 ort 3 . e 18C 24C27 p3.0Cp3 i/o p3.0 to p3.7 are bidirectional port pins with internal pull-up resistors. p pins that have 1s written to them ar e pulled high by the internal pull-up resistors, and in that state can be used as inputs. as inputs, port 3 pins being pulled externally low source current because of the internal pull-up resistors when driving a 0-to-1 output transition, a strong pull-up is active for one cor clock period of the instruction cycle. port 3 pins also have the various secondary functions described below. 16 18 p3.0/rxd receiver data for uart serial port. 17 19 p3.1/txd transmitter data for uart serial port. 18 20 p3.2/ int0 r 0. external interrupt 0. this pin can also be used as a gate control input to time 19 21 p3.3/ int1 external interrupt 1. this pin can also be used as a gate control input to timer 1. 22 24 p3.4/t0 timer/counter 0 external input. 23 25 p3.5/t1 timer/counter 1 external input. 24 26 p3.6/ wr external data memory write strobe. this pin latches the data byte from port 0 into an external data memory. 25 27 p3.7/ rd external data memory read strob e. this pin enables the data from an external data memory to port 0.
aduc845/aduc847/aduc848 rev. b | page 13 of 108 pin no: 52-mqfp pin no: 56- lfcsp mnemonic type 1 description 20, 34, 48 22, 36, 51 dv dd s digital supply voltage. 21, 35, 47 7, 38, 50 23, 3 dgnd s digital ground. 26 28 sclk (i 2 c) i/o 2 c interface. as an input, this pin is a schmitt- in ternal pull-up is present on this pin unless it is low. this pin can also be controlled in software as a digital serial interface clock for the i triggered input. a weak outputting logic output pin. 27 29 sdata i/o al serial data pin for the i 2 c interface. as an input, this pin has a weak intern pull-up present unless it is outputting logic low. 28C31, 39 30C33, 39C p2.0Cp2.7 i/o irectional port with internal pull-up resistors. port 2 pins that 2 pins being pulled 36C 42 port 2 is a bid have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs . as inputs, port externally low source current because of the internal pull-up resistors. port 2 emits the middle and high-order address bytes during accesses to the 24-bit external data memory space. port 2 pins also have the various secondary functions described below. 28 30 p2.0/sclock (spi) l pull-up is present on this pin unless it is serial interface clock for the spi interface. as an input this pin is a schmitt- triggered input. a weak in terna outputting logic low. 29 31 p2.1/mosi serial master output/slave input data fo r the spi interface. a strong interna pull-up is present on this pin when the spi interface outputs a logic high. strong internal pull-do l a wn is present on this pin when the spi interface outputs a logic low. 30 32 p2.2/miso master input/slave output for the spi inte rface. a weak pull-up is present on this input pin. 31 33 p2.3/ss /t2 interface. a weak pull-up is present on this pin. nabled, counter 2 is incremented in response to a negative slave select input for the spi for both package options, this pin can also be used to provide a clock input to timer 2. when e transition on the t2 input pin. 36 39 p2.4/t2ex control input to timer 2. when enabled, a negative transition on the t2ex input pin causes a timer 2 capture or reload event. 37 40 p2.5/pwm0 0 output appears at this pin. if the pwm is enabled, the pwm 38 41 p2.6/pwm1 if the pwm is enabled, the pwm1 output appears at this pin. 39 42 p2.7/pwmclk provided at this pin. if the pwm is enabled, an exte rnal pwm clock can be 32 34 xtal1 i input to the crystal oscillator inverter. 33 35 xtal2 o n output from the crystal oscillator inverter. see the hardware desig considerations section for a description. 40 43 ea external access enable, logic input. wh en held high, this input enables the to ss is available on the aduc845, device to fetch code from internal program memory locations 0000h f7ffh. no external program memory a cce aduc847, or aduc848. to determine the mode of code execution, the ea pin is sampled at the end of an external re set assertion or as part of a device power cycle. ea can also be used as an external emulation i/o pin, and therefore the voltage level at this pin must not be changed during normal operation because this might cause an emulation interrupt that halts code execution. 41 44 psen o cution. program store enable, logic output. this function is not used on the aduc845, aduc 847, or aduc848. this pin remains high during internal program exe psen can also be used to enable serial download mode when pulled lo through a resistor at the end of an external reset assertion or as part o device power cycle. w f a 42 45 ale o te ing external data memory access cycles. it can be address latch enable, logic output. this output is used to latch the low by (and page byte for 24-bit data address space accesses) of the address to external memory dur disabled by setting the pcon.4 bit in the pcon sfr.
aduc845/aduc847/aduc848 rev. b | page 14 of 108 pin no: 52-mqfp pin no: 56- lfcsp mnemonic type 1 description 43C46, 49C52 46C49, 52C 55 p0.0Cp0.7 i/o rain bidirectional i/o port. port 0 pins that have 1s written to them float, and, in that state, can be used as high impedance inp uts. an external pull-up resistor is required on p0 outputs to force a valid logic high level externally. port 0 is also the multiplexed low-order address and data bu s during accesses to external data memory. in this application, port 0 uses strong internal pull-ups when emitting 1s. these pins are part of port 0, which is an 8-bit open-d 1 i = input, o = output, s = supply.
aduc845/aduc847/aduc848 rev. b | page 15 of 108 general description uc84 7, 848 are singl le, ips, 8052 core upgr es to the aduc834 and aduc836. they include additional analog inputs for applications requiring more adc channels. the aduc845, aduc847, and aduc848 are complete smar transducer front ends. the family integrates high resolution - adcs with flexible, up to 10-channel, input multiplexing, a ast 8-bit mcu, and program and data flash/ee memory on a gle chip. the aduc845 includes two (primary and auxiliary) 24-bit - adcs with internal buffering and pga on the primary adc. the aduc847 includes the same primary adc as the aduc845 (auxiliary adc removed). the aduc848 is a 16-bit adc version of the aduc847. the adcs incorporate flexible input multiplexing, a temperature sensor (aduc845 only), and a pga (primary adc only) allowing direct measurement of low-level signals. the adcs include on-chip digital filtering and programmable output data rates that are intended for measuring wide dynamic range and low frequency signals, such as those in weigh scale, strain gage, pressure transducer, or temperature measurement applications. l up to 12.58 mips performance while maintaining 8051 instruction set compatibility. the available nonvolatile flash/ee program memory options are 62 kbytes, 32 kbytes, and 8 kbytes. 4 kbytes of nonvolatile flash/ee data memory and 2304 bytes of data ram are also provided on-chip. the program memory can be configured as data memory to give up to 60 kbytes of nv data memory in data logging applications. on-chip factory firmware supports in-circuit serial download and debug modes (via uart), as well as single-pin emulation mode via the ea the ad 12.58 m 5, aduc84 and aduc e-cyc ad t the devices operate from a 32 khz crystal with an on-chip pl generating a high frequency clock of 12.58 mhz. this clock is routed through a programmable clock divider from which the mcu core clock operating frequency is generated. the micro- controller core is an optimized single-cycle 8052 offering f sin pin. the aduc845, aduc847, and aduc848 are supported by the quickstart? development system featuring low cost software and hardware development tools.
aduc845/aduc847/aduc848 rev. b | page 16 of 108 watchdog timer 2304 bytes user ram power supply monitor temp sensor 200 a 200 a band gap reference v ref detect av dd agnd dv dd dgnd eset r por mo s i mi s o ss xta l 1 a d u c 8 4 5 adc c t - ? adc c c a p r i m a r y a d 2 4 - b i o n t r o l and l i b r a t i o n dac dac control 12-bit voltage output dac t0 t1 t2ex t2 int0 int1 ea psen ale sin g le- p in e m ulator txd rx d 4 k b y t e s d a t a / flash/ee 62 kbytes program/ flash/ee uart serial port current source mix single- cycle 8052 mcu core d o w d e n l o a d e r b u g g e r spi serial interface 16-bit counter timers wake-up/ rtc timer pll with prog. clock divider xta l 2 osc 2 d a t a p o i 1 1 - b i t s t a c k n t e r s p o i n t e r ain mux ain1 ain2 mux pwm0 pwm1 pwm control uart timer sc lk sc lk s data i 2 c serial interface 04741-004 pga buf buf 56 4 36 51 23 37 38 50 18 17 19 44 43 45 30 31 32 33 28 29 34 35 21 20 39 33 25 24 41 pwmcl k 42 40 14 5 6 22 1 ain3 2 ain4 3 ain5 9 ain6 10 ain7 11 ain8 12 p0.0 ( ad0) p0.1 ( ad1) 46 47 p0.2 ( ad2) 48 p0.3 ( ad3) 49 p0.4 ( ad4) 52 p0.5 ( ad5) 53 p0.6 ( ad6) 54 p0.7 ( ad7) 55 p3.0 ( r xd) p3.1 ( t xd) 18 19 p3.2 ( i nt0) 20 p3.3 ( i nt1) 21 p3.4 ( t 0) 24 p3.5 ( t 1) 25 p3.6 ( w r) 26 p3.7 ( rd) 27 p1.0/ain1 p1.1/ain2 56 1 p1.2/ain3/refin2+ 2 p1.3/ain4/refin2 ? 3 p1.4/ain5 9 p1.5/ain6 10 p1.6/ain7/iexc1 11 p1.7/ain8/iexc2 12 6 ) p 2 .0 /s clk (a8 / a1 p2.1/m osi ( a 9/a17) 30 31 p2.2/m iso ( a 10/a18) 32 p2.3/ss/t2 ( a 11/a 19) 33 p2.4/t2ex ( a 12/a 20) 39 p2.5/pw m 0 ( a 13/a 21) 40 p2.6/pw m 1 ( a 14/a 22) 41 p2.7/pw m c l k ( a 15/a 23) 42 ain9 15 ain10 16 a incom/da c 13 dual 16-bit - ? dac dual 16-bit pwm adc c o n t r and c a l i b r a t i o o l n auxiliary adc 24-bit - ? adc refin+ 8 refin? 7 iexc1 11 iexc2 12 notes 1. the pin numbers refer to the lfcsp package only. f i g u re 4. d e t a il ed b l o c k d i ag r a m of t h e a d uc8 45
aduc845/aduc847/aduc848 rev. b | page 17 of 108 watchdog timer 2304 bytes user ram power supply monitor 200 a 200 a band gap reference v ref detect av dd agnd dv dd r eset por mo s i mi s o ss xta l 1 aduc847 adc control and calibration dac dac control 12-bit voltage output dac t0 t1 t2ex t2 int0 int1 ea psen ale sin g le- p in e m ulator txd rx d 4 kbytes data/ flash/ee 62 kbytes program/ flash/ee uart serial port current source mix single- cycle 8052 mcu core downloader debugger spi serial interface 16-bit counter timers wake-up/ rtc timer pll with prog. clock divider xta l 2 osc 2 data pointers 11-bit stack pointer ain mux ain1 ain2 mux pwm0 pwm1 pwm control uart timer sc lk sc lk s data i 2 c serial interface 04741-070 pga buf buf 56 4 36 51 23 dgnd 37 38 50 18 17 19 44 43 45 30 31 32 33 28 29 34 35 21 20 39 33 25 24 41 pwmcl k 42 40 14 5 6 22 1 ain3 2 ain4 3 ain5 9 ain6 10 ain7 11 ain8 12 p0.0 ( ad0) p0.1 ( ad1) 46 47 p0.2 ( ad2) 48 p0.3 ( ad3) 49 p0.4 ( ad4) 52 p0.5 ( ad5) 53 p0.6 ( ad6) 54 p0.7 ( ad7) 55 p3.0 ( r xd) p3.1 ( t xd) 18 19 p3.2 ( i nt0) 20 p3.3 ( i nt1) 21 p3.4 ( t 0) 24 p3.5 ( t 1) 25 p3.6 ( w r) 26 p3.7 ( rd) 27 p1.0/ain1 p1.1/ain2 56 1 p1.2/ain3/refin2+ 2 p1.3/ain4/refin2 ? 3 p1.4/ain5 9 p1.5/ain6 10 p1.6/ain7/iexc1 11 p1.7/ain8/iexc2 12 p 2 .0 /s clk (a8 / a1 6 ) p2.1/m osi ( a 9/a17) 30 31 p2.2/m iso ( a 10/a18) 32 p2.3/ss/t2 ( a 11/a 19) 33 p2.4/t2ex ( a 12/a 20) 39 p2.5/pw m 0 ( a 13/a 21) 40 p2.6/pw m 1 ( a 14/a 22) 41 p2.7/pw m c l k ( a 15/a 23) 42 ain9 15 ain10 16 a incom/da c 13 dual 16-bit - ? dac dual 16-bit pwm refin+ 8 refin? 7 iexc1 11 iexc2 12 primary adc 24-bit - ? adc notes 1. the pin numbers refer to the lfcsp package only. f i g u re 5. d e t a il ed b l o c k d i ag r a m of t h e a d uc8 47
aduc845/aduc847/aduc848 rev. b | page 18 of 108 watchdog timer 2304 bytes user ram power supply monitor 200 a 200 a band gap reference v ref detect av dd agnd dv dd dgnd r eset por mo s i mi s o ss xta l 1 aduc848 adc control and calibration dac dac control 12-bit voltage output dac t0 t1 t2ex t2 int0 int1 ea psen ale sin g le- p in e m ulator txd rx d 4 kbytes data/ flash/ee 62 kbytes program/ flash/ee uart serial port current source mix single- cycle 8052 mcu core downloader debugger spi serial interface 16-bit counter timers wake-up/ rtc timer pll with prog. clock divider xta l 2 osc 2 data pointers 11-bit stack pointer ain mux ain1 ain2 mux pwm0 pwm1 pwm control uart timer sc lk sc lk sd a t a i 2 c serial interface 04741-072 pga buf buf 56 4 36 51 23 37 38 50 18 17 19 44 43 45 30 31 32 33 28 29 34 35 21 20 39 33 25 24 41 pwmcl k 42 40 14 5 6 22 1 ain3 2 ain4 3 ain5 9 ain6 10 ain7 11 ain8 12 p0.0 ( a d0) p0.1 ( a d1) 46 47 p0.2 ( a d2) 48 p0.3 ( a d3) 49 p0.4 ( a d4) 52 p0.5 ( a d5) 53 p0.6 ( a d6) 54 p0.7 ( a d7) 55 p3.0 ( r xd) p3.1 ( t xd) 18 19 p3.2 ( i nt0) 20 p3.3 ( i nt1) 21 p3.4 ( t 0) 24 p3.5 ( t 1) 25 p3.6 ( w r) 26 p3.7 ( r d) 27 p1.0/ain1 p1.1/ain2 56 1 p1.2/ain3/refin2+ 2 p1.3/ain4/refin2 ? 3 p1.4/ain5 9 p1.5/ain6 10 p1.6/ain7/iexc1 11 p1.7/ain8/iexc2 12 p2.0/sc l k ( a 8/a 16) p2.1/m osi ( a 9/a17) 30 31 p2.2/m iso ( a 10/a18) 32 p2.3/ss/t2 ( a 11/a 19) 33 p2.4/t2ex ( a 12/a 20) 39 p2.5/pw m 0 ( a 13/a 2 1) 40 p2.6/pw m 1 ( a 14/a 2 2) 41 p2.7/pw m c l k ( a 15/a 23) 42 ain9 15 ain10 16 a incom/da c 13 dual 16-bit - ? dac dual 16-bit pwm refin+ 8 refin? 7 iexc1 11 iexc2 12 primary adc 16-bit - ? adc notes 1. the pin numbers refer to the lfcsp package only. f i g u re 6. d e t a il ed b l o c k d i ag r a m of t h e a d uc8 48 8052 instr u c t ion se t t a b l e 4 do c u me n t s t h e n u m b er o f clo c k c y cles r e q u ir e d fo r e a ch in st r u c t io n. m o st inst r u c t io n s ar e exe c u t e d i n o n e o r t w o c l oc k c y c l es r e s u l t in g in 12. 58 mip s p e ak p e r f o r mance w h e n o p e r a t i n g a t p llc o n = 0 0 h. timer oper a t io n t i m e rs o n a s t anda r d 8052 in cr em en t b y o n e wi th e a c h mac h ine c y c l e . on th e aduc845, aduc847, a nd adu c 848, o n e machi n e c y cle is e q ual t o o n e cl o c k c y cle; t h er efo r e , t h e t i m e rs in cr em en t a t t h e s a me ra t e as t h e co r e c l o c k. ale on t h e aduc8 34, th e ou t p u t on t h e ale p i n is a c l o c k a t 1/6t h o f th e co r e o p er a t in g f r eq uen c y . on t h e aduc8 45, aduc847, a nd adu c 848, th e ale p i n o p era t es as f o l l o w s. f o r a sin g le machi n e c y cle in s t r u c t io n, ale is hig h fo r t h e e n ti r e m a c h i n e a c h i n e cy c l e i n s t ru c t i o n , a l e i s hi gh fo r t h e f i rs t machin e c y cle a nd t h e n lo w fo r t h e r e ma inder o f t h e machi n e c y cl es . external memor y a c cess the adu c 845, aduc847, and aduc848 do no t s u p p o r t e x te r n a l pro g r a m me mor y a c c e ss , b u t t h e p a r t s c a n a c c e ss up to 16 mb (24 addres s b i ts) o f ext e r n al da t a m e m o r y . w h en acces s in g ex t e r n al r a m, t h e ew ait r e g i s t er mig h t n e e d t o b e p r og ra mm e d i n o r der t o g i v e ext r a machi n e c y c l es t o mo vx co mman d s t o al lo w f o r dif f er in g ext e r n al ram acces s s p e e ds. cy c l e . f o r a t w o o r m o r e m
aduc845/aduc847/aduc848 rev. b | page 19 of 108 c o mple te sfr map reserved r e s e r v e d reserved r e s e r v e d reserved reserved reserved r e s e r v e d reserved r e s e r v e d not used reserved reserved reserved spicon f8h 05h dacl fbh 00h dach aduc845 only aduc845 only aduc845 only aduc845 only aduc845 only aduc845 only aduc845 only fch 00h daccon fdh 00h reserved b f0h 00h i2cadd1 f2h 7fh r e s v e d e r v e d r e s e r reserved i2ccon h 00h gn0 l 2 gn0 m 2 gn0 h 2 gn1 l 2 gn1 e9h xxh eah xxh ebh xxh ech xxh edh e 8 h 2 xxh reserved reserved acc e0h 00h of0l e1h xxh of0m e2h xxh of0h e3h xxh of1l e4h xxh o f 1 e5h adc0con2 e6h 00h h xxh a d c s t a t d8h 00h adc0l 00h d9h adc0m dah 00h adc0h dbh 00h adc1m dch 00h a d c ddh 00h ad c1l deh 00h 1 h psw a d c d0h 00h m o de d1h 08h a dc0c d 2 h o n1 07h ad c1 c o n d3h 00h sf d4h 45h icon d5h 00h reserved t2con c8h 00h rcap2l cah 00h rcap2h cbh 00h tl2 cch 00h th2 cdh 0 0 h reserved wdcon c0h 10h ip b8h 00h ec o n b9h 00h edata1 bch 00h e d a t bdh a 2 0 0 h ie a8h 00h ie a9h ip 2 a 0 h p2 a0h ffh sc o n 00h 98h sbuf 99h 00h i2cdat 9ah 00h p1 90h f f h tc on 88h 00h tmod 89h 00h tl0 8ah 00h tl1 8bh 00h th0 8ch 00h th1 8dh 0 0 h p0 h ffh 8 0 sp 81h 07h dpl 82h 00h dph 83h 00h dpp 84h 00h r e s e r v e d r e s e r ffh spidat s e r v e d h deh edarl c6h 00h edata3 beh 00h d a t a 4 h 00h pcon h 00h v e d p3 b0h f7h 0 0 h r e psmcon d f e b f 8 7 ispi ffh 0 wcol feh 0 spe fdh 0 spim fch 0 c p o fbh l 0 cpha fah spr1 f9h 0 spr0 f8h 0 bits f7h 0 f6h 0 f5h 0 f4h 0 f3h 0 f2h f1h 0 f0h 0 bits mdo efh 0 eeh 0 mco edh 0 ech 0 ebh 0 eah e9h bits 0 e8h 0 e7h 0 e6h 0 e5h 0 e4h 0 e3h 0 e2h e 1 h 0 e0h 0 bits rdy0 dfh 0 rdy1 deh 0 cal ddh 0 noxref dch 0 err0 dbh 0 err1 dah d9h 0 d8h 0 bits cy d7h 0 ac d6h 0 f0 d5h 0 rs1 d4h 0 rs0 d3h 0 ov d2h fi d1h 0 p d0h 0 bits tf2 cfh 0 ceh 0 e x f 2 rclk cdh 0 tclk cch 0 exen2 cbh 0 tr2 cah cnt2 c9h 0 c8h 0 bits cap2 pre3 c7h 0 c6h p r e 2 0 pre1 c5h 0 c4h 1 wdir c3h 0 wds c2h wde c1h 0 c0h 0 wdwr bits bfh 0 beh 0 p a d c pt2 bdh 0 ps bch 0 pt1 bbh 0 px1 bah pt0 b9h 0 px0 bits b8h 0 rd b7h 1 wr b6h 1 t1 b5h 1 t0 b4h 1 int1 b3h 1 int0 b2h txd b1h 1 rxd b0h 1 bits ea afh aeh eadc et2 adh es ach 0 et1 abh 0 ex1 aah et0 a9h 0 ex0 a8h 0 bits a7h a 6 h a 5 h 1 a4h 1 a3h 1 a2h a 1 h 1 a0h 1 bits sm0 9fh 0 sm1 9eh 0 sm2 9dh 0 ren 9ch 0 tb8 9bh 0 rb8 9ah ti 99h 0 98h 0 ri bits 97h 1 96h 1 95h 1 94h 1 93h 1 92h t2ex 91h 1 t2 bits 90h 1 tf1 8fh 0 8eh tr1 0 tf0 8dh 0 tr0 8ch 0 ie1 8bh 0 it1 8ah ie0 89h 0 it0 88h 0 bits 87h 1 86h 1 85h 1 84h 1 83h 1 82h 81h 1 80h 1 bits 1 1 0 1 0 1 ie0 89h 0 it0 88h 0 tcon 88h 00h bit mnemonic bit address reset default bit value mnemonic t v a l u e sfr address these bits are contained in this byte. r m a p k e y : n o t e : s w h o s e a d d r e s s e s e n d i n 0 h o r 8 h a r e s m a i n t a i n t h e i r p r e - r e s e t v a l u e s a f t e r = 1 . 1 reserved r e s e r d 0 0 0 0 0 0 0 0 0 00 1 ti m e c o n hthse c 1 se c 1 mi n 1 ho u in t v a l co n a1h a2h a 3 h a4h a5h a6h h 00h 00h 00h 00h 00h 00h r e s e t d e f a u l s f s f r s f r b i t a d d r e s s a b l e . 1 t h e s e s f r 2 a r e s e t i f t i m e c o n . 0 calibration coefficients are preconfigured on power-up to factory calibrated values. v e d r e s e r v e 0 1 r 1 dp a 7 00h r e s e r reserved reserved reserved reserved pw mc o n aeh 00h g8 4 5 /7 /8 00h reserved s e r v e d t3 f t3 c o n 9dh 9 e h 00h a i t h 00h h pw m 1 l p w m 1 h sph 00h 00h 00h 00h 00h b1h b2h b 3 h b4h reserved reserved h i p i d h 00h i2cm reserved pre0 h 53h mdi i2crs i2ctx i2ci i2cadd 9bh 55h 04741-073 not available on aduc848 aduc845 only f i g u re 7 . e a d uc84 5, a d uc 84 7, a n d a d uc8 48 v e d reserved c f b 7 h a f h r e d 00h ew 9 f pw m 0 l p w m 0 reserved c c2h a0h edarh c 7 mde pllcon d 7 c o m p let e sfr m a p f o r t h
aduc845/aduc847/aduc848 rev. b | page 20 of 108 nal description instruction set . optimized single-cycle 8051 instruc escription ytes ycles 1 functio 8051 table 4 tion set mnemonic d b c arithmetic a a,rn add register to a 1 1 add a,@ri add indirect memo ry to a 1 2 add a,dir add direct byte to a 2 2 add a,#dat a add immediate to a 2 2 addc a,rn add register to a with c arry 1 1 addc a,@ri add indirect memory to a wi th carry 1 2 addc a,dir ith carry add direct byte to a w 2 2 add a,#data add immediate to a with car ry 2 2 subb a,rn subtract register from a with borrow 1 1 subb a,@ri subtract indirect memory from a with borrow 1 2 subb a,dir subtract direct from a with borro w 2 2 subb a,#data subtract immediate from a with bor row 2 2 inc a increment a 1 1 inc rn increment register 1 1 inc @ri increment indirect memory 1 2 inc dir increment direct byte 2 2 inc dptr increment data pointer 1 3 dec a decrement a 1 1 dec rn decrement register 1 1 dec @ri decrement indirect memory 1 2 dec dir decrement direct byte 2 2 mul ab multiply a by b 1 4 div ab divide a by b 1 9 da a decimal adjust a 1 2 logic anl a,rn and register to a 1 1 anl a,@ri and indirect memory to a 1 2 anl a,dir a nd direct byte to a 2 2 anl a,# data iate to a and immed 2 2 anl dir,a and a to direct b yte 2 2 anl dir, #data ediate data to direct byte and imm 3 3 orl a,rn or register to a 1 1 orl a,@ ri to a or indirect memory 1 2 orl a,di r or direct byte to a 2 2 orl a,#da ta or immediate to a 2 2 orl dir,a or a to direct byte 2 2 orl dir,#d ata irect byte or immediate data to d 3 3 xrl a,rn exclusive-or register to a 1 1 xrl a,@ri exclusive-or indirect me mory to a 2 2 xrl a,#data exclusive-or immediate to a 2 2 xrl dir,a e xclusive-or a to direct byte 2 2 xrl a,dir exclusive-or indirect memory t o a 2 2 xrl d ir,#data data to direct exclusive-or immediate 3 3 clr a clear a 1 1 cpl a complement a 1 1 swap a swap nibbles of a 1 1 rl a r otate a left 1 1
aduc845/aduc847/aduc848 rev. b | page 21 of 108 mnemonic description bytes cycles 1 rlc a rotate a left through carry 1 1 rr a rotate a right 1 1 rrc a rotate a right through carr y 1 1 data t ransfer mov a,r n move register to a 1 1 mov a,@ri move indirect memory to a 1 2 mov r n,a move a to register 1 1 mov @ri,a move a to indirect memor y 1 2 mov a,dir move direct byte to a 2 2 mov a,#da ta move immediate to a 2 2 mov rn,#d ata move register to immediate 2 2 mov dir,a move a to direct byte 2 2 mov rn, dir move register to direct byte 2 2 mov dir, rn move direct to register 2 2 mov @ri,#data move immediate to indirect memory 2 2 mov dir,@ri move indirect to direct memory 2 2 mov @ri,dir m ove direct to indirect memory 2 2 mov dir,dir te to direct byte move direct by 3 3 mov dir,#data move immediate to direct byte 3 3 mov dptr,#data move immediate to data pointer 3 3 movc a,@a+dptr move code byte relative dptr to a 1 4 movc a,@a+pc move code byte relative pc to a 1 4 movx 2 a,@ri move external (a8) data to 1 4 a movx 2 a,@dptr move external (a16) data t 1 4 o a movx 2 @ri,a move a to externa l data (a 8) 1 4 movx 2 @ dptr,a move a to external data (a 16) 1 4 pu dir push direct byte sh onto stac k 2 2 pop dir pop direct byte f rom stack 2 2 xch exchange a and register 1 1 a,rn xc a,@ri ex h change a and indirect m emory 1 2 xc d a,@ri h exchange a and indirect m emory nibble 1 2 xc h a exchange a and direct by ,dir te 2 2 boolean clr c clear carry 1 1 clr bit clear direct bit 2 2 setb c set carry 1 1 setb bit set direct bit 2 2 cpl c complement carry 1 1 cpl bit complement dir ect bit 2 2 anl c,bit and direct bit and carry 2 2 anl c,/bit and direct bit in verse to c arry 2 2 orl c,bit or direct bit a nd carry 2 2 orl c,/bit or direct bit inverse to car ry 2 2 mov c,bit move direct bit t o carry 2 2 mov bit,c move carry to direct bit 2 2 branching jmp @a+dptr jump indirect relative to d ptr 1 3 ret return from subr outine 1 4 reti return from int errupt 1 4 acall addr11 absolute jump to subrout ine 2 3 ajmp addr11 absolute jump u nconditio nal 2 3 footnotes at end of table.
aduc845/aduc847/aduc848 rev. b | page 22 of 108 mnemoni ption c descri bytes cycles 1 sjmp rel short jump (relative addre ss) 2 3 jc rel jump on carry = 1 3 2 jnc rel jump on carr y = 0 2 3 jz rel jump on accu mulator = 0 2 3 jnz rel jump on accu mulator ! = 0 2 3 djnz rn,rel decrement r egister, jnz r elative 2 3 ljmp long jump unconditional 3 4 lcall 3 addr16 long jump to subroutine 3 4 jb bit,rel jump on direct bit = 1 3 4 jnb bit,rel jump on direct bi t = 0 4 3 jbc bit,rel jump on direct bit = 1 and clear 3 4 cjne a,dir,rel compare a, direct jne rela 4 tive 3 cjne a,#data,rel compare a, immediate jn e relative 3 4 cjne rn,#data,rel compare register, immedi ate jne relative 3 4 cjne @ri,#data,rel compare indirect, immed iate jne relative 3 4 djnz dir,rel decrement direct byte, jn z relative 3 4 miscellaneous nop no operation 1 1 1 one cycle is one clock. 2 movx instructions are four cycles when they have 0 wait state. cycles of movx instructio ait. 3 lcall instructions are three cycles when the lcall instruction comes from an interrupt. memory organization the aduc845, aduc847, and aduc848 contain four memory blocks: ? 62 kbytes/3 h/ee program memory assume the 62-kbyte option. when ea ns are 4 + n cycles when they have n wait states as programmed via ew 2 kbytes/8 kbytes of on-chip flas memory ? 4 kbytes of on-chip flash/ee data memory ? 256 bytes of general-purpose ram ? 2 kbytes of internal xram flash/ee program memory the parts provide up to 62 kbytes of flash/ee program memory to run user code. all further references to flash/ee program is pulled high externally during a power cycle or a hardware reset, the parts default to code execution from their internal 62 kbytes of flash/ee program memory. the parts do not support the rollover from internal code space to external code space. no external code space is available on the parts. permanently embedded firmware allows code to be serially downloaded to the 62 kbytes of internal code space via the uart serial port while the device is in-circuit. no external hardware is required. during run time, 56 kbytes of the 62-kbyte program memory can be reprogrammed. this means that the code space can be upgraded in the field by using a user-defined protocol running on the parts, or it can be used as a data memory. for details, see the nonvolatile flash/ee memory overview section. ecial function register (sfr) space. for details, see tile flash/ee memory overview section. os ram e r s divided into two separate er a e lower 128 bytes of ram. the e the lower 128 bytes of internal data memory are mapped as shown in figure 8. the lowest 32 bytes are grouped into four banks of eight registers addressed as r0 to r7. the next 16 bytes (128 bits), locations 20h to 2fh above the register banks, form a block of directly addressable bit locations at bit addresses 00h to 7fh. the stack can be located anywhere in the internal memory address space, and the stack depth can be expanded up to 2048 bytes. reset initializes the stack pointer to location 07h. any call or push pre-increments the sp before loading the stack. therefore, loading the stack starts from location 08h, which is also the first register (r0) of register bank 1. thus, if one is going to use more than one register bank, the stack pointer should be initialized to an area of ram not used for data storage. flash/ee data memory the user has 4 kbytes of flash/ee data memory available that can be accessed indirectly by using a group of registers mapped into the sp the nonvola general-purp e the general-purpos am i memories, the upp nd th lower 128 bytes of ram can be accessed through direct or indirect addressing. the upper 128 bytes of ram can be accessed only through indirect addressing because it shares th same address space as the sfr space, which must be accessed through direct addressing.
aduc845/aduc847/aduc848 rev. b | page 23 of 108 11 10 01 00 07 h 1f h 00 h 08 h 0f h 17 h 10 h 18 h 2f h 20 h 7f h 30 h four banks of eight registers r0 to r7 bit-addressable (bit addresses) area banks selected via bits in psw general-purpose reset value of stack pointer 04741-008 f i gure 8. l o wer 1 2 8 b y tes of i n te rna l d a ta m e m o r y inte rnal xr am the adu c 845, aduc847, and aduc848 co n t a i n 2 k b yt es o f on - c h i p e x te nd e d d a t a me mor y . t h i s me mor y , a l t h ou g h o n - chi p , is ac cess e d v i a t h e mo v x in st r u c t io n. t h e 2 k b y t es o f in t e r n al xr a m a r e ma p p e d i n to t h e b o t t o m 2 k b yt es o f t h e ext e r n al addr ess s p ace if t h e c f g84x.0 (t a b le 7) b i t is s e t; o t h e r w is e , access t o the ext e r n al da ta m e m o r y o c c u rs j u s t li k e a s t anda r d 8051. e v en w i t h t h e c f g84x.0 b i t s e t, acces s t o t h e exter n al (o f f chi p ), xram o c c u rs on ce the 24-b i t dptr is g r ea t e r t h a n 0007ffh. external data memory space (24-bit a d s p d r e s s a c e ) 000000h ffffffh cfg845/7/8.0 = 0 external data memory space (24-bit address space) 000000h ffffffh cfg845/7/8.0 = 1 0007ffh 000800h 2 kbytes on-chip xram 04741-009 f i gure 9. intern a l a n d e x tern a l xr a m w h en ena b le d and w h e n acces s i n g t h e i n t e r n al xr am, t h e p0 a nd p2 p o r t p i n o p era t io n s , as w e l l as t h e rd a nd wr st rob e s , do n o t op era t e as a s t anda rd 8051 m o vx in s t r u c t io n. this al lo ws t h e us er to us e t h es e p o r t p i n s as s t a n da r d i/o . the in ter n a l xr a m ca n b e co nf igure d as p a r t o f t h e ex tende d 11 -b i t st ack p o in t e r . by defa u l t, t h e st ack o p era t es ex ac t l y li k e a n 805 2 in tha t i t r o l l s o v er f r o m ffh t o 00h in t h e g e n e ral - p u r p os e ram. on t h e aduc845, aduc847, a nd adu c 848, h o wev e r , i t f g 8 4 5 . 7/aduc847.7 / aduc848.7) t o e r s s a r y t o ext e n d t h e 8-b i t s t ack p o in t e r i n t h e s p s f r in t o a n 11- b i t st ack p o i n t e r . is p o s s i b le ( b y s e t t in g c ena b le t h e 11 -b i t ext e n d e d s t ack p o in t e r . i n t h is cas e , t h e s t ack r o l l s o v er f r o m ffh in ram t o 0100h in xram. the 11- b i t st ack p o in t e r is vis i b l e in t h e s p h and s p s f rs. t h s p s f r is lo ca t e d a t 81 h as wi t h a s t anda r d 80 52. the s p h s f is lo ca t e d a t b7 h. th e 3 ls bs of t h e sp h s f r c o n t a i n t h e 3 ext r a b i t s ne c e upper 1792 bytes of on-chip xram (data + stack for exsp = 1, data only for exsp = 0) cfg845/7/8.7 = 0 256 bytes of on-chip data ram (data + stack) lower 256 bytes of on-chip xram (data only) 00h ffh 00h 07ffh 100h 04741-010 cfg845/7/8.7 = 1 f i g u re 10. e x tend e d st ack p o i n te r o p er at ion m m e mo r y acces s t o t h e r , s t like a standa r d 8051-co m p a t ib le co r e , t h e 84 8 ca n acces s exter n al da t a o v t r u c t io n. t h e mo vx i n st r u c t io n u t o ma tic a l l y o u t p u t s t h e va r i ous co n t r o l s t r o bes r e q u ir e d t o w e ve r , c a n a c c e ss up to h i s i s a n e n h a n c e m e n t of y e r n y s p ac e a v ai lab l e on a n d a r d 8051-c o m p a t e t h e h a r d war e desig n n s ider a s e c t io n a c c e r n t er mig h t n e e d b e pro g mme d to g x t ch i n o v x p era t ion. this is t o acco un t d i f f er i e x t e r n a l r a m access p eed s . a i t s f r r a ddr ess: w e r - o n u l t: d dr es e: p ecial f u nc tio n r e g i s t er (s fr), wh en p r og ra mm e d , dic t a t es t h e n u m b er o f wa i t s t a t es fo r t h e mo vx i n s t r u c t io n. the val u e can v a r y b e tw e e n 0h a nd 7h. the mo vx in st r u c - t i o n i n cr e a s e s b y o n e machin e c y cle (4 + n , w h er e n = e w ait n u m b er in de ci mal) fo r e v er y i n cr e a s e i n t h e ew ait val u e . ex t e r n al d a ta memor y (ex t ernal xr am) ther e is n o su pp o r t fo r ext e r n al p r og ra p a r t s. h o w e v e j u aduc845/adu c 847/adu c m e m o r y usin g a m x i n s a a c c e ss t h e d a t a me mor y . t h e p a r t s , ho 16 mb yt es o f ext e r n al da t a m e m o r y . t t h e 64 k b t e s o f e x t a l d a t a me mo r s t a i b le co r e . s e c o t io n s f o r det a i l s. w h en s s i n g ext e al r a m, t h e ew ai t r e g i s to r a i ve e r a m a e c y cl es to t h e m o f o r n g s ew s f p o def a 9f h 00h bi t a s a b l n o this s
aduc845/aduc847/aduc848 rev. b | page 24 of 108 e r s ( s f r s) s s i n g o n ly . i t r n t h e c p u and a l l o n -ch i p p e r i ph - m in g t h e p r o g ra mm i n g mo d e l o f t h e 4 7 / c 84 8 via t h e s f r a r ea is sh o w n in f i gur e 11. h e fo ur p u g i d e i n t h e s f r a r e a . the s f r i sters i n n t a r e g i sters t h a t p r o v ide a n in t e r f a c e b erals. special fu nc t i o n r e g i s t the s f r s p ace is ma p p e d in t o t h e u p p e r 128 b y t e s o f in t e r n al d a t a m e m o r y sp ace an d ac cess e d b y dir e c t a d d r e p r o v ide s a n in te f ace b e twe e era l s. a b l o c k d i a g r a s h o w aduc845/adu c 8 a d u al l r e g i s t ers exc e p t t h e p r og ra m co un t e r (pc) and t g e n e ral - r p os e r e s t er b a n k s r e s i r e g cl ud e c o r o l, co nf igur a t io n, and d a t e tw e e n t h e c p u a n d all o n -c hi p p e r i ph 128-byte special function register area 62-kbyte electrically reprogrammable nonvolatile flash/ee program m e m o r y 8051- compatible c o r e o t h e r o n - c h i p r c e s wdt psm tic pwm peripherals temperature sensor c u r r e n t s o u 12-bit dac serial i/o - ? adc 4-kbyte electrically reprogrammable nonvolatile flash/ee data memory 256 bytes ram 2kbytes xram 04741-011 f i g u re 11. p r og r a m m ing m o d e l acc u m u l a to r s f r (a c c ) a c c is t h e accum u la t o r r e gist e r , w h ich is us e d f o r ma t h op e r a - ti o n s in c l ud i n g a d di ti o n , s u b t racti o n , in t e g e r m u l t i p li ca ti o n a n d divisio n , and b o ole a n b i t ma n i p u la t i on s. t h e mn e m onics fo r acc u m u l a to r - sp e c if ic i n st r u c t ion s u s ua l l y refer to t h e acc u m u l a to r a s a . b sfr (b) the b r e g i s t er is us e d w i t h t h e acc u m u l a t o r fo r m u l t i p li ca t i o n a nd division o p er a t io n s . f o r o t h e r inst r u c t io n s , i t can b e t r e a te d as a genera l-p u r p os e s c ra tch p a d r e g i st er . f t h r e e 8-b i t r e g i st ers: d p p (p a g e p p , c c 848 s u p p o r t d u al da ta u al p o i n t e rs s e c t io n. s t ac k p o i n t e r ( s p an d s p h ) r a r es s of t h e sta c k . the s p r e g i st e r i n cr e m e fo r e u s h a nd c a ll e x e c u t i o n s . a l th o u gh r a m, t h e s p r e g i st e r i h i s ca us es t h e s t ack t o b e g a s m e n t ion e d e a rlier , t d e d 11-b i t st ack in t e r . th r e e ext r t ack in t e r a r e t h r e e l o a b le t h e s f r , t h r w i s e, sf om. o g r a m status w o rd e p s w s n st a t u s of t h e c p u as l i s f r a ddr ess: p o w e r - o n def a u l t: bi t a d dr es s a b l e: a bl e 5. psw sfr b i t desig n ati o ns bit no . name description d a ta p o inter ( d p t r) the da t a p o in t e r is made u p o b y t e ), d p h (hig h b y te), an d d p l (lo w b y te). these p r o v ide m e m o r y addr ess e s fo r in ter n a l co de and da t a m e m o r y access. the dpt r can b e mani p u la te d as a 16-b i t r e g i ster (dptr = dph , dpl ) , a l t h ou g h i n c dp tr i n st r u c t ions a u toma t i c a l l y ca r r y o v er t o d p p , o r as thr e e in dep e nden t 8-b i t r e g i s t e r s ( d d p h, d p l). the adu c 8 4 5 / a d u 847/adu p o in t e rs. s e e t h e d d a t a the s p s f r is t h e st ack p o i n t e r , w h ich is us e d to h o ld a n in t e r n a l m a d d c a l l e d t h e top i s n t e d b e d a t a is sto r e d d u r i n g p t h e s t a c k c a n r e s i d e a n y w h e r e i n o n - c h i p s i n i t ia li z e d t o 07h a f t e r a r e s e t. t i n a t lo c a t i o n 08h. h e p a r t s o f fer a n ext e n p o e t h a b i ts n e e d e d t o mak e u p t h e 11 -b i t s p o t h e s bs o f t h e s p h b y t e lo c a te d a t b7 h . t e n s p h e ex s p (cfg84x.7) b i t m u s t b e s e t; ot he t h e sph r c a n b e ne i t he r w r i tte n to nor re a d f r pr (psw ) t h f r c o n t a i s s e v e ra l b i ts t h a t r e f l e c t t h e c u r r en t s t e d i n t a bl e 5 . d0h 00h y e s t 7 cy c a r r y f l ag . 6 ac au x i l i a r y c a r r y f l a g . 5 f0 g e ner a l-p u r pose f l ag . 4, 3 rs1, rs0 r e g i ster bank s e lec t bits . rs1 rs0 s e lec t ed bank 0 0 0 0 1 1 1 0 2 1 1 3 2 ov o v er flow f l ag . 1 f1 g e ner a l-p u r pose f l ag . 0 p p a rit y bit.
aduc845/aduc847/aduc848 rev. b | page 25 of 108 power control register (pcon) the pcon sfr contains bits for power-saving options and general-purpose status flags as listed in table 6. sfr address: 87h power-on default: 00h bit addressable: no table 6. pcon sfr bit designations bit no. name description 7 smod double uart baud rate. 0 = normal, 1 = double baud rate. 6 seripd serial power-down inte rrupt enable. if this bit is set, a serial interrupt from either spi or i 2 c can terminate the power-down mode. 5 int0pd int0 power-down interrupt enable. if this bit is set, either a level ( it0 = 0) or a negative-going transition ( it0 = 1) on th int0 pin terminates power-down mode. e 4 aleoff if set to 1, the ale output is disabled. 3 gf1 general-purpose flag bit. 2 gf0 general-purpose flag bit. 1 pd power-down mode enable. if se part enters power-down mode. t to 1, the 0 ----- not implemented. write dont care. aduc845/aduc847/aduc848 configuration register (cfg845/cfg847/cfg848) the cfg845/c fg847/cfg848 sfr contains the bits necessary to configure the internal xram and the extended sp. by default, 48. sfr address: afh it configures the user into 8051 mode, that is, extended sp, and the internal xram are disabled. when using in a program, use the part name only, that is, cfg845, cfg847, or cfg8 power-on default: 00h bit addressable: no table 7. cfg845/cfg847/cfg848 sfr bit designations bit no. name description 7 exsp extended sp enable. if this bit is set to 1, the stack rolls over from sph/sp = 00ffh to 0100h. if this bit is cleared to 0, sph sfr is disabled and the stack rolls over from sp = ffh to sp = 00h. 6 ---- not implemented. write dont care. 5 ---- not implemented. write dont care. 4 ---- not implemented. write dont care. 3 ---- not implemented. write dont care. 2 ---- not implemented. write dont care. 1 ---- not implemented. write dont care. 0 xramen if this bit is set to 1, the internal xram is mapped into the lower 2 kbytes of the external address space. if this bit is cleared to 0, the internal xr is accessible and up to 16 mb of external am data memory become available. see figure 8.
aduc845/aduc847/aduc848 rev. b | page 26 of 108 e ilable on the auxiliary adc on the aduc845). the parts also incorporate d ns. s lly, ut ranges from 20 mv to 2.56 v (v 1.024). buffering the input channel es . re, puts. table 8 and table 9 show the allowable external resistance/ capacitance values for unbuffered mode such that no gain error at the 16-bit and 20-bit levels, respectiv used with internal buffering enabled, it is recommended that a ry to if the reference range is av dd . this accounts for the restricted common-mode input range in the buffer. some circuits, for example, bridge circuits, are tly suitable to use without having to offset where the v ref /2 and is not sufficiently t on the auxiliary adc (aduc845 only). the auxiliary .50 v. o 24 bits on the aduc845 and the aduc847, and up to 16 bits on the aduc848 of no mis g codes performance (20 hz update rate, chop enabled). the - modulator converts the sampled ains ta conversion result at program- able output rates. the signal chain has two modes of operation, chop enabled and chop disabled. the chop adc circuit information the aduc845 incorporates two 10-channel (8-channel on th mqfp package) 24-bit -? adcs, while the aduc847 and aduc848 each incorporate a single 10-channel (8-channel on the mqfp package) 24-bit and 16-bit -? adc. each part also includes an on-chip programmable gain amplifier and configurable buffering (neither is ava digital filtering intended for measuring wide dynamic range an low frequency signals such as those in weigh-scale, strain-gage, pressure transducer, or temperature measurement applicatio the aduc845/aduc847/ad uc848 can be configured as four or five (mqfp/lfcsp package) fully-differential input channel or as eight or ten (mqfp/lfcsp package) pseudo differential input channels referenced to aincom. the adc on each part (primary only on the aduc845) can be fully buffered interna and can be programmed for one of eight inp ref means that the part can handle significant source impedanc on the selected analog input and that rc filtering (for noise rejection or rfi reduction) can be placed on the analog inputs if the adc is used with internal buffering disabled (adc0con1.7 = 1, adc0con1.6 = 0), these unbuffered inputs provide a dynamic load to the driving source. therefo resistor/capacitor combinations on the inputs can cause dc gain errors, depending on the output impedance of the source that is driving the adc in ely, is introduced. when capacitor (10 nf to 100 nf) be placed on the input to the adc (usually as part of an antialiasing filter) to aid in noise performance. the input channels are intended to convert signals directly from sensors without the need for external signal conditioning. with internal buffering disabled (relevant bits set/cleared in adc0con1), external buffering might be required. when the internal buffer is enabled, it might be necessa offset the negative input channel by +100 mv and to offset the positive channel by ?100 mv inheren output voltage is balanced around large to encroach on the supply rails. internal buffering is no available adc (aduc845 only) is fixed at a gain range of 2 the adcs use a - conversion technique to realize up t sin input signal into a digital pulse train whose duty cycle cont the digital information. a sinc 3 programmable low-pass filter (see table 28) is then used to decimate the modulator output data stream to give a valid da m bit in the dcmode register enables or disables the chopping scheme. table 8. maximum resistance for no 16-bit gain error (unbuffered mode) external capacitance a gain 0 pf 50 pf 100 pf 500 pf 1000 pf 5000 pf 1 111.3 k? 27.8 k? 16.7 k? 4.5 k? 2.58 k? 700 ? 2 53.7 k? 13.5 k? 8.1 k? 2.2 k? 1.26 k? 360 ? 4 25.4 k? 6.4 k? 3.9 k? 1.0 k? 600 ? 170 ? 8C128 10.7 k? 2.9 k? 1.7 k? 480 ? 270 ? 75 ? table 9. maximum resistance for no 20-bit gain error (unbuffered mode) external capacitance gain 0 pf 50 pf 100 pf 500 pf 1000 pf 5000 pf 1 84.9 k? 21.1 k? 12.5 k? 3.2 k? 1.77 k? 440 ? 2 42.0 k? 10.4 k? 6.1 k? 1.6 k? 880 ? 220 ? 4 20.5 k? 5.0 k? 2.9 k? 790 ? 430 ? 110 ? 8C128 8.8 k? 2.3 k ? 1.3 k ? 370 ? 195 ? 50 ?
aduc845/aduc847/aduc848 rev. b | page 27 of 108 signal cha i n o v er vie w ( c hop enab led , chop = 0) w i th th e c hop b i t = 0 ( s ee th e a d cmo d e s f r b i t de sig n a - t i o n s i n t a b l e 2 4 ), t h e ch o p ping s c h e me is enab le d . this is t h e defa u l t co nd i t ion an d g i ves op t i m u m p e r f o r ma n c e in ter m s o f o f fs et er r o rs a n d dr if t p e r f o r ma n c e . w i t h ch op ena b le d , t h e a v a i la b l e o u t p u t ra t e s va r y f r o m 5.35 h z t o 105 h z (s f = 255 a nd 13, r e s p e c t i v e l y). a typ i ca l b l o c k di a g ra m of t h e ad c i n p u t cha nnel w i t h cho p ena b le d is sho w n i n f i gur e 1 2 . t h e s a m p l i ng f r e q u e nc y of t h e mo d u l a tor l o op i s m a n y t i me s hig h er t h an t h e b a ndwi d t h o f t h e in pu t sig n a l . th e in t e g r a t o r i n t h e mo d u la t o r s h a p es t h e q u an t i za t i o n n fr o m th e a n al o g - t o- d i gi ta l c o n v e r s i o n ) so t h a t th e n o i s e i s p u s h e to w a rd o n e - h a l f of t h e mo d u l a t o r f r e q u e nc y . t h e output of t h e - mo d u la t o r fe e d s dir e c t l y in t o t h e dig i t a l f i l t er . the dig i t a l f i l t er th e n band-limi t s t h e r e sp o n s e t o a f r e q ue n c y sig n if ican tly lo w e r tha n on e-half o f th e m o d u la t o r f r e q uen c y . i n t h is ma nn e r , t h e 1 - bit output of t h e c o m p ar ator i s t r ansl a t e d i n to a b a nd limi t e d, lo w n o is e o u t p u t f r o m t h e ad cs. the ad c f i l t er is a lo w-p a ss si n c 3 o r (sin x/x) 3 f i l t er w h os e p r i m a r y f u n c t i on i s t o re mo ve t h e quan t i za t i on n o is e i n t r o d u c e d a t t h e m o d u l a tor . the c u to f f f r eq uen c y a nd d e c i ma te d o u t p ut da t a ra t e o f t h e f i l t er a r e p r og ra mma b l e v i a t h e sin c f i l t er w o r d lo ade d i n t o t h e f i l t er (s f) r e g i s t er (s e e t a b l e 28 ). the co m p lete sig n a l cha i n is ch o p p e d , r e su l t i n g in exc e l l en t dc o f fs et a nd o f fs et dr if t sp e c i f ica t io n s and is ext r em e l y b e n e f i cia l in a p pli c a - t i o n s w h er e dr if t, n o i s e r e j e c t io n, an d o p t i m u m emi r e j e c t ion are i m p o r t a n t . w i t h de c i ha ve re su w o r d f i lte r t o t h fac t o r is r e s t r i c t ed t o a n 8 - b i t r e g i s t er cal l ed s f (s ee t a b l e 2 8 ) , e a c t u al d e ci m a ti o n f a ct o r i s t h e r e g i s t e r v a l u e t i m e s 8 . ther efo r e , t h e de cima t e d o u t p ut ra t e f r o m t h e sin c 3 f i l t er (a nd th e a d c co n v er si o n ra t e ) i s o is e (w hich r e s u l t s d ch o p e n a b l e d , t h e ad c r e pea t edl y r e v e r s es i t s in p u t s . th e m a te d d i g i t a l o u t p u t w o r d s f r o m t h e si n c 3 f i l t er , t h er efo r e , a p o s i t i ve of f s e t and a ne g a t i ve of f s e t te r m i n c l u d e d . a s a l t , a f i na l su mming st age is inc l u d e d s o t h a t e a ch out p u t f r o m t h e f i l t er is s u mm e d a nd a v er a g e d w i t h t h e p r e v io u s out p ut to pro d u c e a ne w v a l i d output re s u lt to b e w r itte n e ad c da t a r e g i s t er . p r og ra mmin g t h e si nc 3 de cima t i o n t h mod adc f sf f = 8 1 3 1 w h er e: f ad c is t h e a d c co n v ersio n r a t e . sf is t h e de cimal e q ui v a len t o f t h e w o r d lo ade d t o t h e f i l t er re g i ste r . f mo d is th e m o d u la t o r s a m p lin g ra t e o f 32.768 kh z. the ch o p ra t e of t h e chann e l is half t h e o u t p u t da t a ra t e : adc chop f f = 2 1 a s sho w n i n t h e b l o c k di a g ra m (f igur e 12), t h e sin c 3 fi l t e r output s a l t e r n a t ely c o n t a i n + v os a nd ?v os , w h e r e v os is t h e re sp e c t i ve ch a n n e l of f s e t . sinc 3 filter pga 3 ? ? t chann e l wit h chop e n ab led f i g u re 12. bl ock d i ag r a m o f t h e a d c i n p u
aduc845/aduc847/aduc848 rev. b | page 28 of 108 s o f fs e t i d b y p e r f o r min g a r g a v era 2. s a v era g e e an s t h a t t h e s e t t li n g o a n y e i n g ra mmin e ad c is t w ice t h e n o l c o n v e r t i m e , l e an asy o us st ep chan ge o n t h l og in p o t r e f l ect e h e th i r d s u b s eq uen t t . s e e 13. t h i s r e m o v e u nn i n g e o f t h i b y 2 m t i m e t c h a n g p r o g o f t h r m a s i o n w h i n ch r o n e a n a u t is n full y d un til t o u t p u f i gur e adc adc settle t f t = = 2 v e r s i o n tim e in cr ease s b y 0. 73 2 m s f o r e a ch increm en t i n 2 e a l lo wa b n g e f o r s o p ena b 1 3 t o i th f a u l t o f es p o n d n v e r s i t e s, nd p e e a k n o r f o r ma a r e sho b l e 10, t a , ta b l e 1 n d t a b l e h e n u m a r e c a l an d r a te d a t a r en t i a l i o l t a g e v a nd a co mm on- m o d e v o l t a g e o f 2.5 v . n o t e t h a t t h e con - s f . t h l e r a f (c h l e d ) i s 2 5 5 w a d e 69 (45h). th e c o r r i n g c o o n r a r m s a a k - to -p i s e p e n c e s w n i n t a b l e 1 1 2 , a 1 3 . t b e r s ty p i g e n e d i f f e n p u t v o f 0 sample 1 n o / i n v a l i d output s a m p l e 2 s a m p l e 3 s a m p l e 4 s a m p l e 5 sample 6 sample 1 + sample 2 valid output 2 s a m p l e 5 + s a m p valid output 2 l e 6 sample 2 + sample 3 v a l i d o u 2 t p u t s y n c ( i . e . h r o n o u n g e h a n n e l g e ) s c h a c h a c n sample 4 + sample 5 v a l i d o u t p 2 u t sample 3 + sample 4 no output 2 04741-012 chop e n ab led f i g u re 13. a d c s e t t ling ti me f o ll o w in g a sy nch r onous c h ang e wit h sample 1 no output s a m p l e 2 s a m p l e 3 s a m p l e 4 s a m p l e 5 sample 6 sample 1 sample 2 valid output 2 sample 5 sample 6 valid output 2 s a m p l e 2 s valid output 2 a m p l e 3 a s n c h u s c h a i s c o n t u s i n p u t g e ) r o n i n u o o n g e c h a n ( i . e . d sample 4 sample 5 2 unsettled output sample 3 sample 4 u n s e t t 2 l e d o u t p u t 04741-014 g ti me f o ll o w in g an a s y n chron o us chang e w i t h chop e n ab led f i g u re 14. a d c s e t t l i n
aduc845/aduc847/aduc848 rev. b | page 29 of 108 adc noise performance with chop enabled ( chop = 0) table 10, table 11, table 12, and table 13 show the output rm noise and output peak-to-peak resolution in bits (rounded to the nearest 0.5 lsb) for some typical output update rates for th aduc845, aduc847, and aduc848. the numbers are typica and are generated at a differential input voltage of 0 v and a common-mode voltage of 2.5 v. the output update rate is selected via the sf7 to sf0 bits in the sf filter register. it is important to note that the peak-to-peak resolution figures represent the resolution for which there is no code flicker within a 6-sigma limit. the outp s e l ut noise comes from two sources. the first source is the electrical noise in the semic uctor devices (device noise) ges. ges, the rms noise numbers are in the same table 10. aduc845 and aduc847 typical output rms noise (v) vs. input range and update rate with chop enabled input range ond used in the implementation of the modulator. the second source is quantization noise, which is added when the analog input is converted to the digital domain. the device noise is at a low level and is independent of frequency. the quantization noise starts at an even lower level but rises rapidly with increasing frequency to become the dominant noise source. the numbers in the tables are given for the bipolar input ran for the unipolar ran range as the bipolar figures, but the peak-to-peak resolution is based on half the signal range, which effectively means losing 1 bit of resolution. sf word data update rate (hz) v 640 mv 1.28 v 2.56 v 20 mv 40 mv 80 mv 160 mv 320 m 13 105.03 1.75 1.30 1.65 1.5 2.1 3.1 7.15 13.3 23 59.36 1.25 0.95 1.08 0.94 1.0 1.87 3.24 7.1 27 50.56 1.0 1.0 0.85 0.85 1.13 1.56 2.9 3.6 69 19.79 0.63 0.68 0.52 0.7 0.61 1.1 1.3 2.75 255 5.35 0.31 0.38 0.34 0.32 0.4 0.45 0.68 1.22 table 11. aduc845 and aduc847 typical peak-to-peak resolution (bits) vs. input range and update rate with chop enabled input range sf word data update rate (hz) 20 mv 40 mv 80 mv 160 mv 320 mv 640 mv 1.28 v 2.56 v 13 105.03 12 13 14 15 15.5 16 16 16 23 59.36 12 13.5 14.5 15.5 16.5 16.5 17 16.5 27 50.56 12.5 13.5 15 16 16.5 17 17 17.5 69 19.79 13 14 15.5 16 17.5 17.5 18 18 255 5.35 14.5 15 16 17 18 18.5 19 19.5 table 12. aduc848 typical output noise (v) vs. input range and update rate with chop enabled input range sf word data update rate (hz) 20 mv 40 mv 80 mv 160 mv 320 mv 640 mv 1.28 v 2.56 v 13 105.03 1.75 1.30 1.65 1.5 2.1 3.1 7.15 13.3 23 59.36 1.25 0.95 1.08 0.94 1.0 1.87 3.24 7.1 27 50.56 1.0 1.0 0.85 0.85 1.13 1.56 2.9 3.6 69 19.79 0.63 0.68 0.52 0.7 0.61 1.1 1.3 2.75 255 5.35 0.31 0.38 0.34 0.32 0.4 0.45 0.68 1.22 table 13. aduc848 typical peak-to-peak resolution (bits) vs. input range and update rate with chop enabled input range sf word data update rate (hz) 20 mv 40 mv 80 mv 160 mv 320 mv 640 mv 1.28 v 2.56 v 13 105.03 12 13 14 15 15.5 16 16 16 23 59.36 12 13.5 14.5 15.5 16 16 17 16 27 50.56 12.5 13.5 15 16 16 16 16 16 69 19.79 13 14 15.5 16 16 16 16 16 255 5.35 14.5 15 16 16 16 16 16 16
aduc845/aduc847/aduc848 rev. b | page 30 of 108 signal cha i n o v e r vie w wi th c h op disable d ( chop = 1) wi t h ch o p = 1, ch o p is dis a b l e d an d t h e a v a i la b l e o u tp u t r a t e s va r y f r o m 16.06 h z t o 1.365 kh z. th e ra n g e o f a p p l ic a b le s f w o r d s is f r o m 3 t o 255. w h en swi t c h in g betw e e n c h a n ne ls wi t h c h o p dis a b l e d , t h e c h ann e l t h r o ug h p u t r a t e is hig h er tha n w h ch o p is enab le d . the d r a w b a c k w i th c h o p d i sa b l e d i s th a t th e d r i f t pe rf o r m a n c e i s d e gra d ed and o f fs et ca l i b r a t io n is r e q u ir e fol l o w in g a ga i n ra n g e cha n ge or sig n if ica n t t e m p era t ur e cha n ge. a b l o c k di a g r a m o f t h e ad c i n p u t channel wi t h ch o p dis a b l e en d d is sh o w n i n f i gur e 15 . c t o r is r e s t r i c t ed t o a n 8 - b i t r e g i s t er s f ; the ac t u al decima t i o n fr o m t h e s i n c f i l t er (a nd t h e a d c co n v ersio n ra t e ) is t h er efo r e the s i g n a l chai n i n cl u d e s a m u l t i p l e x or b u f f er , p g a, - m o d u l a to r , an d dig i t a l f i l t er . the m o d u la to r b i t st r e a m is a p plie d to a sinc 3 f i l t er . pr o g ra mming t h e si n c 3 de cim a t i o n f a fac t o r is t h e r e g i s t er val u e t i m e s 8. the de c i ma t e d o u t p u t ra t e 3 mod adc f 1 sf 8 f = e: is t h e a d v ersio n r a t e . t h e de ci ui v a len t o f t h lo ade e f i l t er t er , valid ran r o m 3 t o 255. d is th e m o d u la t o r s a m p lin g ra t e o f 32.768 kh z. r . c a us e t h e a s w h er f ad c c co n sf i s r e g i s mal e q g e is f e w o r d d t o t h f mo the s e t t l i n g t i me t o a s t ep in p u t is g o v e r n e d b y t h e dig i t a l f i l t e a syn c hr o n ized s t ep c h a n g e r e q u ir es a s e t t l i n g t i me o f thr e e t i m e s t h e p r o g r a mme d up da te r a te; a ch a n n e l cha n ge can b e tr e a t e d as a sy nc hr o n ize d st ep c h a n g e . this is o n e con v ersio n lo n g er t h a n t h e cas e fo r ch o p ena b le d . h o w e v e r , b e a d c th r o ug h p u t i s th r e e tim e s fa s t e r w i t h ch o p d i sa b l e d th a n i t is wi th ch o p ena b led , t h e ac t u a l tim e t o a s e t t le d ad c ou t p u t is sig n if ican tl y less als o . this m e an s tha t fol l o w ing a sy n c hr o n ize d s t ep cha n ge , t h e ad c r e q u ir es t h r e e co n v ersio n s (n o t e : da t a i s not output fo l l o w i n g a s y nch r o n i z e d a d c ch a n ge u n t i l d a t a h s e tt l e d ) b e f o re t h e re su lt a c c u r a tely re f l e c t s t h e n e w i n put vol t age. adc adc settle t f t = = 3 3 an un sy n c hr o n ize d st ep c h a n ge r e q u ir es fo ur co n v ersio n s t o acc u r e n e w a n a l og in p u t a t i t s ou t p ut. n o t e t h a t n s d c a d u e s t n d s o m u s s e t t le s in t t. i n, t h is is one co n v ersion lo n g er t h a ch o p d , b u t a use th e th r o u g h i t h c h o p b l ed is f t h an c h o p e d , th e a c m e ta k e b ta i n a l e d c o u t p u s s . the al l o wab l e ran g e f o r s f is 3 t o 255 wi t h a def a u l t o f 69 ( 4 5 h ). n o is e a r e s h o w n in t a b l e 14, t a ble 15, t a b l e 16, e 1 th n ti a se s m s i n cr s f . a te ly r e f l ec t t h wi t h a n u y n c hr o n i z e h a n g e t h e c co n t i n t o o u t p u da t a a t h e us e r t tak e u n d o u t p u t o acco u n a g a n wi t h e n a b l e be c a d c p u t w d i sa a s t e r w i t h n a b le t u a l t i n t o o s e t t a d t is l e the co r r es p o ndin g con v ersio n ra t e s, r m s, and p e ak-t o - p e a k p e r f o r ma n c e s a n d t a b l f o r ea c h 7 . n o t e th a t e n t in e c o n v e r s i o m e i n c r e b y 0. 24 4 em sinc 3 filter pga 8 ? f i g u re 15. bl ock d i ag r a m of a d c i n pu t chann e l wit h c h o p d i s a b l ed
aduc845/aduc847/aduc848 rev. b | page 31 of 108 e d ( chop adc noise p e r f orma nc e with c h o p d i s a b l = 1) s lut i on i n bit s ( r ou nd e d to t 0.5 p u t u p r a t e s. th e b ers a r e ty a r e g e n e ra t e d a t a dif f l i n p u t a g e o f 0 v and a co mm on- m o d e v o l t a g e o f th e o u t p u t te ra te is s via t h e s f 7 t o s f 0 b i t s i n f f i l t er ste r . n o te t h e a k - t o - p e a k re s o lut i o n s re pre s e n t e so l u ti o n f o c h th e r e i s n o cod e f l i c k e r a 6 - si gm a m i t. uc t o r de vi ces (de v ice n o is e) e i m p l a t o r . e con d n g -p ea k r e so l u tio n is base d o n l e 14. adu n d a d u c 847 t y p i c a l o ut r m s n o i s e (v) v s bl e 1 5 . a d n d a d u c 847 t y p i c a l p a k r e s o l u ti o n (b a d m s n o v s . i n put r a n g e a ) v s . i n p u t r t a b l e 14, t a b l e 15, t a b l e 16, and t a b l e 17 sh o w th e o u t p u t r m noi s e a n d output p e a k - t o - p e a k r e s o th e nea r e s l s b) f o r s o m e typ i cal o u t da t e n u m p i c a l a n d er en t i a v o l t 2 . 5 v . u p da e lec t e d t h e s re g i a t t h e p f i g u r e th e r r wh i w i t h i n l i the o u t p u t n o is e co m e s f r o m tw o s o ur ces. th e f i rs t s o ur ce is t h e e l e c t r i c al n o is e i n t h e s e mic o nd us e d i n t h l em e n t a t i o n o f t h e m o d u t h e s s o ur ce is q u an t i za t i on n o is e , w h ich is a dde d w h e n t h e a n a l o g in p u t is con v er t e d t o t h e dig i t a l do ma i n . t h e d e v i ce n o i s e is a t a lo w le ve l an d is inde p e n d e n t o f f r e q uen c y . th e q u an tiza tion n o i s e s t a r ts a t a n e v en lo w e r l e v e l b u t rise s ra p i dl y w i th in c r e a s i f r e q uen c y to b e co m e t h e do m i na n t n o is e s o urce. the n u m b ers in t h e t a b l es a r e g i v e n fo r t h e b i p o la r in p u t ra n g es. f o r t h e uni p olar ra n g es, t h e r m s n o is e n u m b ers a r e t h e s a m e a s th e b i p o la r ra n g e , b u t t h e p e ak-t o half the sig n al r a n g e , whic h ef fe c t i v e l y m e a n s losin g 1 b i t o f re s o lut i on . t y pi c a l l y , t h e p e r f or m a nc e of t h e a d c w i t h c h op dis a b l e d sh o w s a 0.5 ls b deg r ada t io n o v er t h e p e r f o r ma n c e wi t h ch o p en a b l e d . . i n put r a n g e and u p da t e r a t e w i th c h o p dis a bl e d t a b c 8 4 5 a u t p t a u c 8 4 5 a e a k -t o-p e its) v s . i n p u t r a n g e and u p da t e r a t e w i th c h o p dis a bl e d t a bl e 1 6 . u c 8 4 8 t y p i c a l o u t p ut r i s e (v) n d u p da t e r a t e w i th c h o p dis a bl e d t a bl e 17. adu c 848 t y p i c a l p e a k -t o-p e a k r e s o l u ti o n (b i t s a n g e and u p da t e r a t e w i th c h o p dis a bl e d input r a nge sf w o r d da ta update r a te ( hz) 20 m v 40 m v 8 0 m v 1 6 0 m v 320m v 640m v 1.28 v 2.56 v 3 1365.33 7.5 9 9 9 9 9 9 9 13 315.08 1 1 . 5 1 2 . 5 1 3 . 5 1 4 13.5 14 14 1 4 68 59.36 1 3 1 4 1 4 . 5 1 5 . 5 16 16 16 16 82 49.95 1 3 1 4 1 5 1 6 16 16 16 1 6 255 16.06 1 3 . 5 1 4 . 5 1 5 . 5 1 6 16 16 16 1 6 input r a nge s f w o r d da a t e r a ) 20 mv v 80 mv 0 m v 1.28 v 2.56 v t a u p d te ( h z 4 0 m 160 mv 320 mv 6 4 3 1365.33 30.64 56.18 1 24.5 0 0 . 4 7 2 4 8 . 3 9 4 6 8 . 6 5 7 7 4 . 3 6 1 7 3 9 . 5 13 3 1 5 . 0 8 2.07 1.95 2.28 3 . 2 4 8 . 2 2 1 3 . 9 2 0 . 9 8 4 9 . 2 6 6 8 59.36 0.85 0.79 1.01 0 . 9 9 0 . 7 9 1 . 2 9 2 . 3 3 . 7 82 49.95 0.83 0 . 7 7 0.85 0 . 7 7 0 . 9 1 1 . 1 2 1 . 5 9 3 . 2 255 16.06 0.52 0 . 5 8 0.59 0 . 4 8 0 . 5 2 0 . 5 7 1 . 1 6 1.68 input r a nge s f w o r d p d a t e 20 mv v 80 mv da t a u r a te ( hz) 4 0 m 160 mv 320 mv 640 mv 1.28 v 2.56 v 3 1 3 6 5 . 3 3 7 . 5 9 9 9 9 9 9 9 1 3 3 1 5 . 0 8 11.5 1 3 . 5 1 1 2 . 5 4 13.5 14 14 14 68 59.36 13 14 1 4 . 5 1 5 . 5 17 17 17.5 1 8 8 2 49.95 13 1 4 1 5 1 6 16.5 17.5 18 18 255 16.06 13.5 1 4 . 5 15.5 1 6 . 5 1 7 . 5 1 8 . 5 1 8 . 5 1 9 input r a nge s f w o r d d a t e hz) 20 mv m v 80 mv da t a u p r a te ( 4 0 160 mv 320 mv 640 mv 1.28 v 2 . 5 6 v 3 1 3 6 5 . 3 3 30.64 56.18 1 2 4 . 5 0 0 . 4 7 2 4 8 . 3 9 4 6 8 . 6 5 7 7 4 . 3 6 1 7 3 9 . 5 1 3 3 1 5 . 0 8 2 . 0 7 2.28 3.24 8.22 13.9 20.98 49.26 1 . 9 5 6 9 5 9 . 3 6 0 . 8 5 1.01 0.99 0.79 1.29 2.3 3.7 0 . 7 9 82 49.95 0.83 0.77 0.85 0.77 0.91 1.12 1.59 3.2 255 1 6 . 0 6 0.52 0.58 0.59 0 . 4 8 0 . 5 2 0 . 5 7 1 . 1 6 1.68
aduc845/aduc847/aduc848 rev. b | page 32 of 108 auxiliary adc (aduc845 only) table 18. aduc845 typical output rms noise (v) vs. update rate with chop enabled sf word data update rate (hz) v 13 105.03 17.46 23 59.36 3.13 27 50.56 4.56 69 19.79 2.66 255 5.35 1.13 table 19. aduc845 typical peak-to-peak resolution (bits) update rate vs. 1 with chop enabled sf word data update rate (hz) bits 13 105.03 15.5 23 59.36 18 27 50.56 17.5 69 19.79 18 255 5.35 19.5 1 adc converting in bipolar mode. table 20. aduc845 typical output rms noise (v) vs. update rate with chop disabled sf word data update rate (hz) v 3 1365.33 1386.58 13 315.08 34.94 66 62.06 3.2 69 59.36 3.19 81 50.57 3.14 255 16.06 1.71 table 21. aduc845 peak-to-peak resolution (bits) vs. update rate with chop disabled sf word data update rate (hz) bits 3 1365.33 9 13 315.08 14.5 66 62.06 18 69 59.36 18 81 50.57 18 255 16.06 19 reference inputs the aduc845/aduc847/aduc848 each have two separate differential reference inputs, refin and refin2. while both references are available for use with the primary adc, only refin is available for the auxiliary adc (aduc845 only). the common-mode range for these differential references is from agnd to av dd . the nominal external reference voltage is 2.5 v, with the primary and auxiliary (aduc845 only) reference select bits configured from the adc0con2 and adc1con (aduc845 only), respectively. when an external reference voltage is used, the primary adc sees this internally as a 2.56 v reference (v ref 1.024). ions of lsb size should account for this. v external reference connected and s 45 e lsb 7). the aduc845/aduc847/ad uc848 can also be configured to use the on-chip band gap reference via the xref0/1 bits in the adc0con2 sfr (for primary adc) or the axref bit in adc1con (for auxiliary adc (aduc845 only)). in this mode of operation, the adc sees the internal reference of 1.25 v, thereby halving all the input ranges. a consequence of using th internal ba in peak- n, a load ence ending on the output impedance of ing the reference inputs. reference voltage ntioned above, for example, the ould external decoupling of the refin and/or refin2 inputs is tors that are used to detect a failure in a therefore, any calculat for instance, with a 2.5 using a gain of 1 on a unipolar range (2.56 v), the lsb size i (2.56/2 24 ) = 152.6 nv (if using the 24-bit adc on the aduc8 or aduc847). if a bipolar gain of 4 is used (640 mv), th size is (640 mv)/2 24 ) = 76.3 nv (again using the 24-bit adc on the aduc845 or aduc84 e nd gap reference is a noticeable degradation to-peak resolution. for this reason, operation with an external reference is recommended. in applications where the excitation (voltage or current) for the transducer on the analog input also drives the reference inputs for the part, the effect of any low frequency noise in the excitation source is removed because the application is ratio- metric. if the parts are not used in a ratiometric configuratio low noise reference should be used. recommended reference voltage sources for the aduc845/aduc847/aduc848 include adr421, ref43, and ref192. the reference inputs provide a high impedance, dynamic to external connections. because the impedance of each refer input is dynamic, resistor/capacitor combinations on these pins can cause dc gain errors, dep the source that is driv sources, such as those me adr421, typically have low output impedances, and, therefore, decoupling capacitors on the refin or refin2 inputs w be recommended (typically 0.1 f). deriving the reference voltage from an external resistor configuration means that the reference input sees a significant external source impedance. not recommended in this type of configuration. burnout current sources the primary adc on the aduc845 and the adc on the aduc847 and aduc848 incorporate two 200 a constant current genera connected sensor. one sources current from the av dd to ain(+), and one sinks current from ain( ? ) to agnd. these currents are only configurable for use on ain5/ain6 and/or ain7/ain8 in differential mode only, from the icon.6 bit in the icon sfr (see table 30). these burnout current sources are also available only with buffering enabled via the buf0/buf1 bits in the adc0con1 sfr. once the burnout currents are turned on, a current flows in the external transducer circuit,
aduc845/aduc847/aduc848 rev. b | page 33 of 108 ur e d is r h a s g o n e o p en ci r c ui t. w h en t h e v o l t a g e n dic a t e s t h a t t h e tra n s d u c er has g o n e t a g e is b e lo w a sp e c if ie d t h r e sh ol d , a h e ad c s t a t us r e gis t er (ad c s t a t ), r e c l am p e d , a nd c a l i b r a t i o n r e g i s t e r s a r e n o t f b i t o r d dep e n d s o n w h et h e r h p u t of t h e si nc 3 f i lte r i s a s e c o nd no tch f i lte r e e r e gis t er (ad c mo d e .6). t h e n o t c h is va lid o n l y tc h l og a nd a m e as ur e m e n t o f t h e i n pu t v o l t a g e on t h e a n alog in pu t cha nnel ca n b e t a k e n. w h e n t h e r e su l t in g vol t age m e a s f u l l s c a l e, t h e tra n s d uce m e as ur ed is 0 v , t h i s i sh o r t cir c u i t. th e c u r r en t s o urces w o rk o v er t h e n o r m a l a b s o l u t e in p u t vol t a g e ra n g e sp e c if ica t ion s . reference detec t circuit the ma in and a u xilia r y (aduc845 o n l y ) ad cs ca n be co nf ig - ur e d t o al lo w t h e us e o f t h e in t e r n al b a nd ga p refer e n c e o r a n ext e r n al r e fer e nce t h a t is a p plie d t o t h e refi n p i n s b y m e a n s o f th e xref0/1 b i t in t h e c o n t r o l reg i s t ers ad0co n 2 an d ad1con (ad u c845 o n l y ). a r e f e r e n c e det e c t io n cir c ui t is p r o v id e d t o dete c t w h et h e r a v a lid v o l t a g e is a p plie d t o t h e r e f i n p i n s . t h i s f e a t u r e a r ose i n c o n n ecti o n w i th s t r a i n - g a g e s e n s o r s i n w e ig h s c ales w h er e t h e r e fer e n c e and sig n al a r e p r o v i d ed vi a a ca b l e f r o m th e r e m o t e s e n s o r . i t i s d e s i r a b l e t o de t e c t w h et her t h e cab l e is di s c onn e c t e d . if e i t h e r of t h e pi ns i s f l o a t i n g o r if t h e a p plie d v o l f l a g (no x ref) is set in t co n v ersio n r e s u l t s a u p da t e d if a ca li b r a t i o n is in p r ogr e ss. n o te t h a t t h e re fe re nc e d e te c t d o e s not l o o k a t r e f i n 2 pi ns . i f , d u r i n g ei t h er a n o f fs et o r ga in cal i b r a t ion, t h e n o e x r e b e co m e s act i v e , in di ca tin g a n in co rr ec t v re f , u p da t i ng t h e r e lev a n t ca l i b r a t io n r e g i st er is in hib i te d t o a v o i d lo adin g i n c o r r e c t d a t a in t o t h ese r e gis t er s , a n d t h e a p p r o p r i a t e b i t s in ad c s t a t (e r r 0 o r er r1) a r e s e t . i f t h e u s er ne e d s t o ver if y t h a t a v a li d r e f e r e n c e is in pl ace e v er y t i m e a c a l i b r a t io n is p e r f or me d, t h e st atu s of t h e e r r 0 an d e r r 1 bit s s h ou l d b e ch e c k e d a t t h e e nd o f e v er y ca lib r a t ion c y cle. sinc fil t er register (s f) the n u m b er e n ter e d in t o t h e s f r e g i s t er s e ts t h e de cima t i o n f a c t or of t h e s i n c 3 f i l t er fo r t h e ad c. s e e t a b l e 28 a nd t a b l e 29 . the ra n g e o f o p era t io n o f t h e s f w a d c c h op i s on or of f . w i t h c h op d i s a bl e d , t h e m i n i m u m sf w o r d is 3 a nd t h e maxi m u m is 2 55. this g i v e s an ad c t h r o ug h - p u t ra t e f r o m 1 6 .06 h z t o 1.36 5 kh z. w i t h cho p ena b led , t h e minim u m s f wo r d is 13 (al l val u es lo w e r tha n 13 a r e c l a m p e d t o 13) a n d the maxim u m is 25 5. this g i v e s an ad c thr o u g ra t e o f 5.4 h z t o 105 h z . s e e t h e f ad c eq ua ti o n in t h e ad c des c r i p t io n p r e c e d i n g s e c t ion. a n a d d i t i on a l f e a t u r e pos i ti o n ed in t h e f r eq ue n c y r e s p o n se a t 60 h z . t h i s gi v e s sim u l t an e o us 6 0 h z r e j e c t io n to w h a t e v er n o tch is def i n e d b y t h e s f f i l t er . thi s 60 h z f i l t er is ena b le d v i a t h e rej60 b i t i n t h ad cm o d f o r s f w o r d s 68; o t h e r w is e , ad c er r o rs o c c u r , a n d , t h e n o is bes t us e d wi t h a n s f w o r d o f 82d g i vin g sim u l t a n eo us 50 h z a nd 60 h z r e jec t io n. this f u nc t i o n is us ef u l o n ly wi t h a n ad c c l o c k (mo d u l a t o r ra t e ) o f 32.768 kh z. dur i n g c a lib r a t ion, t h e c u r r en t (us e r - w r i t t e n) val u e o f t h e s f r e g i st er is us e d . -? modul a t o r a - ? ad c usua l l y co n s is ts o f tw o ma i n b l o c k s , a n a n a m o d u l a t o r , an d a dig i tal f i l t er . f o r th e ad uc84 5/aduc847 / aduc848, t h e analog m o d u l a t o r co n s is ts o f a dif f er en ce a m plif ier , a n in teg r a t o r b l o c k, a co m p a r a t o r , and a fe e d b a ck d a c a s s h ow n i n fi g u r e 1 6 . integrator amp comparator difference a nalo g input high f r e q u e n bit stream to digital filter dac c y 04741-016 f i g u re 16. -? m o d u lat o r si mp lif i e d b l ock d i ag r a m i n o p era t ion, t h e a n alog sig n al is fe d t o t h e dif f er en ce am p l i f ier alo n g w i t h t h e ou t p ut f r o m t h e fe e d b a ck d a c. the dif f er en ce b e t w een t h e s e tw o si gnal s i s in t e gra t e d a n d f e d t o t h e co m p a r a t o r . the o u t p u t f r o m t h e com p a r a t o r p r o v ides t h e in p u t t o t h e fe e d - b a ck d a c s o t h e sys t em f u n c t i o n s as a n e ga t i ve fe e d b a ck lo o p a t r . d b y usin g a s u bs e q uen t dig i tal f i l t er s t a g e . th e s a m p lin g f r eq uen c y o f the f t h e h e nd- l i m i te d, l o w noi s e out p ut f r om t h e p a r t . 848 f i l t er is a l o w-p a s s , sin c 3 z d e r e g i ster (ad c mode.6). this 60 h z dr o p -i n no tch fil t e r c a n be th a t tri e s t o mi ni m i z e t h e di f f e r e n ce si gn al . th e d i gi tal d a ta t h r e p r es en ts t h e analog in p u t v o l t a g e is co n t a i n e d in t h e d u ty c y cle o f t h e p u l s e t r ain a p p e a r ing a t t h e out p ut of t h e com p a r a t o this d u ty c y cle d a t a ca n b e r e co ver e d as a d a t a - w o r m o d u la t o r loo p i s m a n y tim e s h i g h e r th a n t h e ba n d w id th o in p u t sig n al . the in t e g r a t o r in t h e m o d u l a t o r sha p es t h e q u a n tiz a ti o n n o i s e (th a t r e s u l t s f r o m th e a n alog- t o- di gi t a l co n v ersio n ) s o t h a t t h e n o is e is p u s h e d t o wa r d o n e- half o f t mo d u l a tor f r e q u e nc y . digit a l fil t er t h e output of t h e - ? mo d u l a t o r f e e d s d i re c t ly i n to t h e d i g i t a l f i l t er . th e dig i t a l f i l t er t h e n b a nd-li mi ts t h e r e sp o n s e t o a f r eq ue n c y si gn i f i c a n tl y lo w e r tha n o n e - h a lf o f th e m o d u la t o r fr e q u e n c y . i n th i s m a n n e r , th e 1- b i t o u t p u t o f th e c o m p a r a t o r i s t r ansl a t e d i n to a b a the adu c 845/aduc847/ad u c or [ ( si nx ) / x ] 3 f i l t er w h os e p r ima r y f u n c t i o n is to r e m o v e t h e q u a n tiz a ti o n n o i s e in tr od uce d a t th e m o d u la t o r . t h e cu t o f f f r e q uen c y a n d de cim a te d o u tpu t d a t a r a te o f t h e f i l t er a r e p r og ra mma b l e v i a t h e s f (si n c f i l t er) s f r as lis t e d i n t a b l e 28 a nd t a b l e 29. f i gure 2 2 , f i gure 2 3 , f i gure 2 4 , and f i g u re 25 sho w t h e f r e q u e n c y re sp ons e of t h e a d c , y i el d i ng a n o v e r a l l output r a te of 1 6 . 6 h wi t h ch o p en a b l e d an d 50 h z w i t h ch o p dis a b l e d . als o det a i l e d in t h es e plo t s is t h e ef fe c t o f t h e f i xe d 60 h z dr o p -in n o t c h f i l t e r (rej60 b i t, ad cm o d e.6). this f i xed f i l t er ca n b e ena b le d o r d i sa b l e d b y set t in g o r c l ea ri n g t h e r e j 6 0 b i t in th e a d c m o
aduc845/aduc847/aduc848 rev. b | page 34 of 108 s ated digital output words from the sinc 3 filter, cluded. as dc so that incor- excellent dc offset and offset ce are ode.3). setting this bit to 1 (logic h cal the /aduc847/aduc848 incorporate four calibration mod adc befo b (ad uring- speci rese dow sfr section. once a user initiates a calibration procedure, the factory frs are overwritten. the adc enable ired may a system calibration facilities. for full calibration to occur on the selected adc, the calibration logic must record the modulator . ration conversion is stored in the offset esult of the n r zero-scale and system full-scale parts, the coefficients are normalized before t - e ed, causing a noxref flag during a calibration, the ce. internal calibration example with chop e should never be required, although a full-scale or gain calibration may be required. however, if a full internal calibration is required, the procedure should be to select a pga gain of 1 (2.56 v) and perform a zero-scale calibration (md2...0 = 100b in the adcmode register). next, select and perform full-scale calibration by setting md2...0 = 101b in the adcmode sfr. now select the desired pga range and perform a zero-scale calibration again (md2..0 = 100b in adcmode) at the new pga range. the reason for the double zero-scale calibration is that the internal calibration procedure for full-scale calibration automatically selects the reference in voltage at pga = 1. enabled for any sf word that yields an adc throughput that i less than 20 hz with chop enabled (sf 68 decimal). adc chopping the adcs on the aduc845/aduc847/aduc848 implement a chopping scheme whereby the adc repeatedly reverses its inputs. the decim therefore, have a positive and negative offset term in a result, a final summing stage is included in each a each output word from the filter is summed and averaged with the previous filter output to produce a new valid output result to be written to the adc data sfrs. the adc throughput or update rate is listed in table 29. the chopping scheme porated into the parts results in drift specifications, and is extremely beneficial in applications where drift, noise rejection, and optimum emi performan important. adc chop can be disabled via the chop bit in the adcmode sfr (adcm hig ) disables chop mode. ibration aduc845 es that can be programmed via the mode bits in the mode sfr detailed in table 24. every part is calibrated re it leaves the factory. the resulting offset and gain cali ration coefficients for both the primary and auxiliary uc845 only) adcs are stored on-chip in manufact fic flash/ee memory locations. at power-on or after a t, these factory calibration registers are automatically nloaded to the adc calibration registers in the parts space. to facilitate user calibration, each of the primary and auxiliary (aduc845 only) adcs have dedicated calibration control sfrs, which are described in the adc sfr interface calibration values that were initially downloaded during the power-on sequence to the adc calibration s the adc to be calibrated must be enabled via bits in the adcmode register. even though an internal offset calibration mode is described in this section, note that the adcs can be chopped. this chopping scheme inherently minimizes offset errors and means that an offset calibration should never be required. also, because factory 5 v/25c gain calibration coefficients are automatically present at power-on, an internal full-scale calibration is requ only if the part is operated at 3 v or at temperatures significantly different from 25c. if the part is operated in chop disabled mode, a calibration need to be done with every gain range change that occurs vi the pga. the aduc845/aduc847/aduc848 ea ch offer internal or output for two input conditions: zero-scale and full-scale points these points are derived by performing a conversion on the different input voltages (zero-scale and full-scale) provided to the input of the modulator during calibration. the result of the zero-scale calib calibration registers for the appropriate adc. the r full-scale calibration conversion is stored in the gain calibratio registers for the appropriate adc. with these readings, the calibration logic can calculate the offset and the gain slope fo the input-to-output transfer function of the converter. during an internal zero-scale or full-scale calibration, the respective zero-scale input or full-scale input is automatically connected to the adc inputs internally. a system calibration, however, expects the system voltages to be applied externally to the adc pins by the user before the calibration mode is initiated. in this way, external errors are taken into account and minimized. note that all aduc845/aduc847/aduc848 adc ca librations are carried out at the user-selected sf word update rate. to optimize calibration accuracy, it is recommended that the slowest possible update rate be used. internally in the being used to scale the words coming out of the digital filter. the offset calibration coefficient is subtracted from the result prior to the multiplication by the gain coefficient. from an operational point of view, a calibration should be treated just like an ordinary adc conversion. a zero-scale calibration (if required) should always be carried out before a full-scale calibration. system software should monitor the relevant adc rdy0/1 bit in the adcstat sfr to determine the end of calibration by using a polling sequence or an interrup driven routine. if required, the noexref0/1 bits can be moni tored to detect unconnected or low voltage errors in the referenc during conversion. in the event of the reference becoming disconnect calibration is immediately halted and no write to the calibration sfrs takes pla nabled, a zero-scale or offset calibration
aduc845/aduc847/aduc848 rev. b | page 35 of 108 i n t c a lib r a t io n a u t o ma t i cal l y this p a e d . a t f o r in ter n al cal i b r a t ion t o b e ef f e c t i v e, th e ain ? pi n e h e l d a t a s t ead y v o l t a g e , wi th in th e allo w a b l e c o mm o n - g du r i ng c a l i br a t i o n . l 1. i e o f 0 v t o t h e s e le c t e d a n alog i b y s e t t in g ... 0 b 11b . a s y s t e m c a l i b r at i o n at t h e r e q u i r e d p g a r a n g e t o b e dif f er en t i al vol t a g es t h a t a r e c a l i b r a t io n dete r m in e s t h e mi d - h) o r 0 v . t h e pr i m ar y a d c i n c o r p or a t e s an on - c h i p pro g r a m m a bl e g a i n a m p r og ra mme d t h r o ug h ei g h t dif f er en t ra n g es , w h ich a r e p r og mm e d vi a t h e ra n g e b i t s (rn0 o rn2) in t h e ad c0con1 r e g i s t er . w i th an ext e r n al 2.5 v fer e n c e a p plie d , t h e uni p ol a r ra n g es a r e 0 mv t o 20 mv , 0 mv t o 40 mv , 0 mv t o 80 mv , 0 mv t o 160 mv , 0 mv t o 320 mv , 0 mv t o 640 mv , 0 v t o 1.28 v a nd 0 v t o 2.56 v , whil e in b i pola r m o d e t h e ra n g es a r e 20 mv , 40 mv , 80 mv , 160 mv , 320 mv , 64 0 mv , 1.28 v , and 2.56 v . th es e ra n g es sh o u l d a p p e a r on t h e i n p u t t o t h e o n -chi p pga. th e a d c ra n g e- ma t c h i n g sp e c if ica t io n o f 2 v (ty p ica l w i t h cho p ena b le d) m e a n s tha t cal i b r a t i o n n eed o n l y be ca rri ed o u t o n a s i n g l e r a nge an d ne e d not b e re p e a t e d w h e n t h e a d c r a nge i s cha n ge d . this is a sig n if ican t a d va n t a g e com p a r e d t o simi la r e o n the ma rk e t . the a u xil i a r y i n t g e ra n g e o n ain(+) is 2. 5 v t o 2.52 v . o h e o t h e r hand , if ai n( ?) is b i as e d t o 2.5 v (a ga in t h e ext e r n al r e fer e n c e v o l t a g e) and t h e ad c is co nf igu r e d fo r a b i p o la r a n a l og in p u t ra n g e o f 1.28 v , th e analog in p u t ra n g e o n t h e ain(+) is 1.22 v t o 3.78 v , tha t is , 2.5 v 1.28 v . the m o des o f op er a t ion fo r t h e ad c a r e f u l l y dif f er en t i a l m o de o r ps eudo dif f er en t i al m o de . i n f u l l y dif f er en t i al m o de , ai n1 t o ain2 a r e on e di f f er en t i al p a ir , and ai n3 t o ai n4 a r e an o t h e r p a ir (ain5 to a i n6, ai n7 to a i n8, an d ain9 to ain10 a r e t h e o t h e rs). i n dif f er en t i al m o de , al l ain( ?) pin nam e s i m ply t h e n e ga ti v e a n alog i n p u t o f th e s e le ct ed d i f f e r e n tial pa i r , th a t i s , ain2, ai n4, ain6, ai n8, ai n10. the t e r m ai n(+) im plies th e posi ti v e i n p u t o f th e se lec t e d di f f e r e n ti al pa i r , th a t i s , a i n 1 , ain3, ai n5, ain7, ai n9. i n ps eudo dif f er en t i a l m o de , e a ch a n a l og in p u t is p a ir e d w i t h t h e ain c o m pin, w h ich can b e b i a s e d u p o r t i e d to a g nd . i n t h is mo de, t h e ain( ?) im p l i e s a i n c om , and ai n(+) i m pl ies an y one o f t h e te n a n a l og i n p u t chan nel s . the co nf igur a t i o n o f t h e in p u ts (uni p o la r vs. b i p o la r ) is sho w n in f i gur e 17. ther efo r e , t h e f u l l -s cale e n d p o s u b t rac t s t h e o f fs et c a lib r a t io n e r r o r , i t is ad vis a b l e t o p e r f o r m a n o f fs et cal i b r a t io n a t t h e s a m e ga in ra n g e as t h a t us ed f o r f u l l - s c ale cal i b r a t io n. ther e is n o p e nal t y t o t h e f u l l - s cale cal i b r a t io n i n re d o i n g t h e z e ro - s c a l e c a l i br a t i o n a t t h e re q u i r e d p g a r a nge beca u s e th e full - s c a le c a li b r a t i o n h a s v e r y g ood m a t c hi n g a t all t h e pga ra n g es . r o c e d ur e a l s o a p plies w h e n ch o p is dis b l n o t e t h s h o u ld b m o d e r a nge to k e e p it f r o m f l o a t i n s y st em c a libr a tion ex a m ple w i t h ch o p enable d , a sy st e m ze r o -s ca le o r o f fs et ca l i b r a t io n s h o u ld n e v e r be r e q u i r ed . h o w e v e r , i f a full - s cale o r g a i n ca l i b r a t io n is r e q u ir e d fo r a n y r e as o n , us e t h e fol l o w in g ty p i ca pro c e d u r e f o r d o i n g s o . a p pl y a dif f er en t al v o l t a g in p u ts (ain+ t o ain?) tha t a r e he ld a t a co mmo n-m o de vol t age. p e r f or m a s y ste m z e ro - s c a l e or of f s e t c a l i br a t i o n b y set t in g t h e m d 2 ... 0 b i t s in t h e a d cmod e reg i s t er t o 1 10b . 2. a p pl y a f u l l -s ca le dif f er en t i al vol t a g e acr o s s t h e ad c in p u ts a g ain a t t h e s a me co mmo n - m o d e v o l t a g e . p e r f or m a s y ste m f u l l - s c a l e or g a i n c a l r a t i o n b t h e m d 2 i t s in t h e a d cmod e reg i s t er t o 1 p e r f o r m us e d si n c e t h e ad c s c ales t o t h e a p plie d t o t h e a d c d u r i n g t h e ca l i b r a t io n r o u t in es . i n b i p o la r mo de, t h e zer o - s ca l e s c ale p o in t o f t h e ad c (800000 progr a mm able gain amplifier l i f i e r ( p g a ) . t h e p g a ca n b e p r a t r e mixe d-sig n al s o l u tio n s a v a i la b l (aduc845 o n l y ) ad c do es n o t in co r p o r a t e a p g a, an d t h e ga in is f i xed a t 0 v t o 2.50 v in uni p ol a r m o de , a n d 2 . 5 0 v bip o l a r m o d e . bipol a r/unipol ar c o nfigur a t ion the a n alog in p u ts o f the adu c 845/adu c 84 7/aduc848 can accep t ei t h er uni p ola r o r b i p o lar in p u t v o l t a g e r a n g es. b i p o la r in p u t r a n g es do n o t im ply t h a t t h e p a r t can hand l e nega t i v e vol t age s wi t h re sp e c t to s y ste m a g nd , b u t r a t h e r wit h re sp e c t o th e n e ga ti v e r e f e r e n c e in p u t . u n i p o l a r a n d b i po la r si gn als o n t h e ain(+) i n pu t o n t h e ad c a r e r e fer e n c e d to t h e v o l t a g e o n t h e r e sp e c t i ve a i n(?) in p u t. ai n(+) a nd ai n(?) r e fer to t h e sig n als s e en b y t h e ad c. f o r exa m p l e , if ain(?) is b i as e d t o 2.5 v (tie d t o th e ext e r n al r e fer e n c e v o l t a g e) a nd t h e a d c is co nf igur e d fo r a uni p ola r a n alog in p u t ra n g e o f 0 mv t o >20 mv , t h e i n pu t v o l t a n t ain1 inp u t 1 aduc845/ aduc847/ aduc848 cs p p ackage aduc845/ aduc847/ aduc848 cs p p ackage inp u t 2 inp u t 3 inp u t 4 inp u t 5 inp u t 6 inp u t 7 inp u t 8 inp u t 9 inp u t 1 0 ain2 ain3 ain4 ain5 ain6 ain7 ain8 ain9 ain10 aincom ain1 ain2 ain3 ain4 ain5 ain6 ain7 ain8 ain9 ain10 fully differential fully differential fully differential fully differential fully differential aincom 04741-017 f i g u re 17. u n ipol ar and bipol a r c h an n e l p a i r s
aduc845/aduc847/aduc848 rev. b | page 36 of 108 when the primary adc is configured for unipolar operation, the output coding is natural (straight) binary with a zero differ- ential input voltage resulting in a code of 000...000, a midscale voltage resulting in a code of 100...000, and a full-scale voltage resulting in a code of 111...111. the output code for any analog input voltage on the main adc can be represented as follows: code C ( ain gain 2 n )/(1.024 v ref ) where: ain is the analog input voltage. gain is the pga gain setting, that is, 1 on the 2.56 v range and 128 on the 20 mv range, and n = 24 (16 on the aduc848). the output code for any analog input voltage on the auxiliary adc can code = ( ain 2 n )/( v ref ) with the same definitions as used for the primary adc above. when the primary adc is conf ured for bipolar operation, the coding is offset binary with negative full-scale voltage resulting in a code of 000...000, a zero differential voltage resulting in a code of 800000, and a positive full-scale voltage resulting in a code of 111...111. the output from the primary adc for any analog input voltage can be represented as follows: code = 2 n ?1 [( ain gain )/(1.024 v ref ) + 1] where: ain is the analog input voltage. gain is the pga gain, that is, 1 on the 2.56 v range and 128 on the 20 mv range. n = 24 (16 on the aduc848). the output from the auxiliary adc in bipolar mode can be represented as follows: code = 2 n ?1 [( ain / v ref ) + 1] excitation currents the aduc845/aduc847/ aduc848 contain two matched, software-configurable 200 a current sources. both source current from av dd , which is directed to either or both of the iexc1 (pin 11 whose alternate functions are p1.6/ain7) or iexc2 (pin 12, whose alternate functions are p1.7/ain8) pins on the device. these currents are controlled via the lower four bits in the icon register (table 30). these bits not only enable the current sources but also allow the configuration of the currents such that 200 a can be sourced individually from both pins or can be combined to give a 400 a source from one or the other of the outputs. these sources can be used to excite external resistive bridge or rtd sensors (see figure 71). adc power-on the adc typically takes 0.5 ms to power up from an initial start-up seque data output coding be represented as follows: ig nce or following a power-down event.
aduc845/aduc847/aduc848 rev. b | page 37 of 108 r acte ristics typical perf orm a n c e c h a ? 120 ? 110 ? 100 ?80 ?70 ? 5 d b) 0 01 0 ?40 ?20 ?10 ?30 ?90 ?60 gain ( 0 2 0 3 0 4 0 5 0 9 0 80 100 70 60 110 frequency (hz) 04741-018 f i g u r e 18. f i lte r r e s p ons e , ch op o n , sf = 69 d eci m a l ? 150 ? 130 ? 110 ?90 ?50 ?30 ? 1 0 ?70 01 0 2 0 3 0 4 0 5 0 9 0 80 100 70 60 frequency (hz) amp l itude (db) 04741-019 f i g u re 19. f i lte r r e s p ons e , ch op o n , sf = 25 5 d e ci ma l ? 120 ? 110 ? 100 ?80 ?70 ?50 ?40 ?20 ?10 ?90 ?30 ?60 0 10 30 50 70 90 110 210 190 170 230 150 130 250 sf (decimal) gain ( d b) 04741-020 ? 120 f i gure 20. 5 0 h z n o rm al mode rej e c t i o n v s . sf w o r d , c h o p o n ? 110 ? 100 ?80 ?70 ?50 ?40 ?30 0 210 190 170 230 250 b) 04741-021 ?20 ?10 ?90 ?60 gain ( d 10 30 50 70 90 110 150 130 sf (decimal) f i gure 21. 6 0 h z n o rm al mode rej e c t i o n v s . sf , chop o n ? 150 ? 130 ? 110 ?90 ?50 ?30 ?10 ?70 170.1 160.1 150.1 140.1 130.1 120.1 110.1 100.1 90.1 80.1 70.1 60.1 50.1 40.1 30.1 20.1 10.1 0.1 frequency (hz) amp l itude (db) 04741-022 10 f i g u re 22. chop o f f , f a dc = 5 0 h z , sf = 52 h ? 150 ? 130 ? 110 ?50 ?10 ?30 ?70 ? 190 10 170.1 160.1 150.1 140.1 130.1 120.1 110.1 100.1 90.1 80.1 70.1 60.1 50.1 40.1 30.1 20.1 10.1 0.1 frequency (hz) amp l itude (db) 04741-023 f i gure 23. chop o f f , sf = 5 2 h, re j6 0 e n abl e d
aduc845/aduc847/aduc848 rev. b | page 38 of 108 ? 120 ? 100 ?80 30 25 20 10 15 5 0 amp ?40 ?60 l itude (db) ?20 0 100 95 90 85 75 70 80 65 60 55 50 40 45 35 04741-024 frequency (hz) f i g u r e 2 4 . cho p on, f a dc = 16 .6 hz , sf = 52h frequency (hz) amp l itude (db) 04741-025 ? 120 ? 100 ?80 ?40 ?60 0 100 95 90 85 75 70 80 65 60 55 50 40 45 35 30 25 20 10 15 abled ?20 5 0 f i gure 25. chop o n , f a dc = 16. 6 h z , sf = 52h, rej60 en
aduc845/aduc847/aduc848 rev. b | page 39 of 108 co trol configured via a number of sfrs that are mentioned here and described in more detail in the followi ng r in ce ame description functional description adc sfr interface the adcs are n led and sections. table 22. adc sf terfa n adcstat adc status register. holds the gener al status of the primary and auxiliary (aduc845 only) adcs. adcmode adc mode register. controls the general modes of operation for primary and auxiliary (aduc845 only) adcs. adc0co n ary adc con onfiguration of the primary adc. 1 prim trol register 1. controls the specific c ad c0con y adc con nfiguration of the primary adc. 2 p rimar trol register 2. controls the specific co ad c1con iliary adc con aux trol register. controls the specific c onfiguration of the auxiliary adc. aduc845 only. sf sinc filter registe only) adc update r. configures the decimation factor for the sinc 3 filter and, therefore, the primary and auxiliary (aduc845 rates. ic on t source co curren ntrol register. allows user c ontrol of the various on-chip current source options. adc0l/m/h primar y adc 24-b lable on the aduc848. it (16-bit on the aduc848) conversion result is held in these three 8-bit registers. adc0l is not avai adc1l/m/h auxiliary adc 24- bit conversion result is held in these two 8-bit registers. aduc845 only. of 0l/m/h -b these three 8-bit registers. of0l is not available on the aduc848. primary adc 24 it offset calibration coefficient is held in of1l/h c 16- auxiliary ad bit offset calibration coefficient is held in these two 8-bit registers. aduc845 only. gn0l/m/h primary adc 24-bit gain cali a duc848. bration coefficient is held in these three 8-bit registers. gn0l is not available on the gn 1l/h xiliary adc 16- au bit gain calibration coefficien t is held in these two 8-bit registers. aduc845 only.
aduc845/aduc847/aduc848 rev. b | page 40 of 108 ster) alibratio n clu derflow fl s. sfr pow bit a tabl bit n adcstat (adc status regi this sfr reflects the status of both adcs including data ready, c in ding refin reference detect and conversion overflow/un address: d8h er-on default: 00h ddressable: yes n, a d various (adc-related) error and warning condit ions ag e 23. ad cstat sfr bit desig nation o. name description 7 ersion or calib y the user, or indirectly by a write to sults to its data or cal rs until the rdy0 bit is cleared. rdy0 ready bit for the primary adc. set by hardware on completion of conv cleared directly b ration. the mode bits, to start calibration. the primary adc is ibration registe inhibited from writing further re 6 adc. auxiliary adc rdy1 ready bit for auxiliary (aduc845 only) same definition as rdy0 referred to the . valid on the aduc845 only. 5 bration. mode bits to start calibration. e sensor selected (auxiliary adc on the aduc845 only) fails to complete. cal calibration status bit. set by hardware on completion of cali cleared indirectly by a write to the note that calibration with the temperatur another adc conversion or 4 primary o u s is flo old. ped to all 1s. on , does not check refin2. noxref no external reference bit (only active if set to indicate that one or both of the refin pin when set, conversion results are clam cleared to indicate valid v r a xiliary (aduc845 only) adc is active). ating or the applied voltage is below a specified thresh ly detects invalid refin ref . 3 result written to t clamped to all 0s or ror conditions that caused the calibration registers not to be written. itiate a c version or calibration. err0 primary adc error bit. set by hardware to indicate that the all 1s. after a calibration, this bit also flags er cleared by a write to the mode bits to in he primary adc data registers has been on 2 finition as err0 referred to the auxiliary adc. valid on the aduc845 only. err1 auxiliary adc error bit. same de 1 CCC not implemented. write dont care. 0 CCC not implemented. write dont care.
aduc845/aduc847/aduc848 rev. b | page 41 of 108 n adcmode (adc mode register) used to control the operational mode of both adcs. sfr address: d1h power-on default: 08h bit addressable: no table 24. adcmode sfr bit designations bit no. ame description 7 C ont care. CC not implemented. write d 6 rej60 hz notch select tting is bit places a notch z, allowing simultaneous 50 hz and 60 hz jection at an sf word of 82 d s 60 hz notch can be set only if sf 68 decimal, that is, the regular ter n h must be 60 hz. th is placed at 60 hz only if the device clock is at 32.768 khz. autom atic 60 bit. se th in the frequency resp onse at 60 h re ecimal. thi fil otc is second notch 5 adc0en imar dc enable. e primary adc and place it in the mode selected in md2Cmd0 below. pr y a set by the user to enable th cleared by the user to place the primary adc into power-down mode. 4 adc1en (a ry (aduc845 only) adc and place it in the mode selected in md2Cmd0 duc845 only) auxiliary (aduc845 only) adc enable. set by the user to enable the auxilia below. cleared by the user to place the auxiliary (aduc845 only) adc in power-down mode. 3 chop chop m t b ode disable . ab se th y the user to le cho llowing a ree times higher adc data t ed with this bit set, giving up to 3 khz adc upda ates. leared the use enable iary (aduc845 only) adc. dis p mode on both the primary and auxiliary hroughput. sf values as lo w as 3 are allow (aduc845 only) adc a 1. te r c by r to chop mode on bo th the primary and auxil pr imar d auxili aduc8 ese select the operation y an ary ( 45 only) adc mode bits. th bits al mo de of the enabled adc as follows: m d2 d1 md0 m 0 0 0 adc po wer-down mode (power-on default). 0 0 1 idle mo dulator are held in a reset state although the modulator clocks are still provided. de. in idle mode, the adc filter and mo 0 1 0 single conversion mode. in single conversi on mode, a single conversion is performed on the enabled adc. upon completion of a conversion, the adc data registers (adc0h/m/l and/or adc1h/m/l (aduc845 only )) are updated. the relevant flags in the adcstat sfr are written, and power-down is re-entered with the md2?md0 accordingly being written to 000. note that adc0l is not available on the aduc848. 0 1 1 continuous conversion. in continuous conv ersion mode, the adc data registers are regularly updated at the selected update rate (see the sinc filter sfr bit designations in table 28). 1 0 0 internal zero-scale calibration. internal short automatically connected to the enabled adc input(s). 1 0 1 internal full-scale calibration. intern al or external refin or refin2 v ref (as determined by xref bits in adc0con2 and/or axref (aduc845 only) in adc1con (aduc845 only) is automatically connected to the enabled adc input(s) for this calibration. 1 1 0 system zero-scale calibration. user should connect system zero-scale input to the enabled adc input(s) as selected by ch3Cch0 and ach3Cach0 bits in the adc0con2 and adc1con (aduc845 only) registers. 2, 1, 0 md2, md1, md0 1 1 1 system full-scale calibration. user should connect system full-scale input to the enabled adc input(s) as selected by ch3Cch0 and ach3Cach0 bits in the adc0con2 and adc1con (aduc845 only) registers.
aduc845/aduc847/aduc848 rev. b | page 42 of 108 adc o le to the aduc845). a write 0 ith no change in contents is also set. he exception to this in the third note of this section.) 1, or if cs are also e other w given e auxilia requested on the primary adc to. only applicable to the ad ? on the other hand, if adc1c n to or adc1en is changed from 0 t , only auxilia is reset. for example, if the pr ary ad is cont converting when the auxiliary adc cha e or en occur rimary adc con than a the auxiliary adc y a into step with the outputs of t m d e r is that the first conversion tim or th uxili adc delayed by up to three output hile uxi y ad update rate is synchronized to e pr ary a . onl applicable to aduc845. if the dc1con wr ccu after the primary adc has co lete ts ope ion, t auxiliary adc can respond im edia y with t havi to fall into step with the primary adcs tput c le. parts are powered down via the pd bit in the pcon register, the current adcmode bits are preserved, that is, they are not reset to default state. upon a subsequent resumption of normal operating mode, the adcs restarts the selected operation defined by the adcmode register. ? once adcmode has been written with a calibration mode, the rdy0/1 (aduc845 only) bits (adcstat) are reset and the calibration commences. on completion, the vant re wn mode. ? any calibration request of the auxiliary adc while the ature sensor is selected fails to complete. although the rdy1 bit is set at the end of the calibration cycle, no update of the calibration sfrs takes place, and the err1 bit is set. aduc845 only. maximum sf (see table 28) ue (slowest adc throughput rate) help to ensure imum calibration. e duration of a calibration cycle is 2/fadc for chop-on de and 4/fadc for chop-off mode. notes on the adcmode register ? any change to the md bits immediately resets both adcs ? if the (auxiliary nly applicab to the md2Cmd bits w treated as a re (see t ? if adc0con is written when adc0en = adc0en is changed from 0 to 1, both ad imm diately r eset. in priority over th ords, the prim ary adc is ry adc and any change is immediately responded uc845. bits in adcstat are written, and the md2 md0 bits a reset to 000b to indicate that the adc is back in power- on is wr itte if do o 1 the ry adc im c inuously temper ng able s, the p tinues undisturbed. rather llow to operate with a phase differ ence from the primar dc, the auxiliary adc falls he pri ary a c. th esult e f e a ary is s w the a liar c th im dc y a ite o rs mp d i rat he m tel ou ng ou yc appropriate calibration registers are written, the rele C ? calibrations performed at val opt ? th mo
aduc845/aduc847/aduc848 rev. b | page 43 of 108 au able 25. adc0con1 sfr bit designations adc0con1 (primary adc control register) adc0con1 is used to configure the primary adc for buffer, unipolar, or bipolar coding, and adc range configuration. sfr address: d2h power-on def lt: 07h bit addressable: no t bit no. name description buffer con . figuration bits buf1 bu tion f0 buffer configura 0 0 adc0+ and adc0? are buffered 0 1 reserved 1 0 buffer bypass 7, 6 buf1, b uf0 1 1 reserved 5 uni primary ad set by the cleared by c unipolar bit. user to enable unipolar coding; ze ro differential input results in 000000h output. the user to enable bipolar coding; zero differential input results in 800000h output. 4 CCC not implem ented. write dont care. 3 CCC not imp lem ented. write dont care. primary ad e ri c rang bits. w tten by the user t o select the primary adc input range as follows: rn2 rn 0 select prim nge (v ref = 2.5 v) 1 rn ed ary adc input ra 0 0 20 mv (0 mv lar mode) 0 C20 mv in unipo 0 0 40 mv (0 mv ar mode) 1 C40 mv in unipol 0 1 80 mv (0 mv lar mode) 0 C80 mv in unipo 0 1 160 m (0 m olar mode) 1 v vC160 mv in unip 1 0 320 m (0 m olar mode) 0 v vC320 mv in unip 1 0 640 m (0 m olar mode) 1 v vC640 mv in unip 1 1 1.28 vC1 mode) 0 v (0 .28 v in unipolar 2, 1, 0 rn2, rn1, rn0 1 1 2.56 vC2.5 1 v (0 6 v in unipolar mode)
aduc845/aduc847/aduc848 rev. b | page 44 of 108 ct register) o. name iption adc0con2 (primary adc channel sele adc0con2 is used to select a reference source and channel for the primary adc. sfr address: e6h power-on default: 00h bit addressable: no table 26. adc0con2 sfr bit designations bit n descr primar y adc exte l reference sel bit. set by the user to enable the primary adc to use the external reference via refin or refin2. cleared by the user to enable the primary adc to use the internal band gap reference (v ref = 1.25 v). rna ect xref1 xref0 0 0 internal 1.25 v reference . 0 1 refin selected. 1 0 refin2 (ain3/ain4) selected. 7, 6 xref1, xref0 1 1 reserved. 5 CCC not implemented. write dont care. 4 CCC not implemented. write dont care. primary adc channel select bits. written by the user to select the primary adc channel as follows: ch3 ch2 ch1 ch0 selected primary adc input channel. 0 0 0 0 ain1Caincom 0 0 0 1 ain2Caincom 0 0 1 0 ain3Caincom 0 0 1 1 ain4Caincom 0 1 0 0 ain5Caincom 0 1 0 1 ain6Cainc om 0 1 0 ain7Caincom 1 0 1 1 ain8Caincom 1 1 0 0 9Caincom (lfcsp package only; not a valid selection on the mqfp age) 0 ain pack 1 0 0 1 ain10Caincom (lfcsp package only; not a valid selection on the mqfp package) 1 0 1 0 ain1Cain2 1 0 1 ain3Cain4 1 1 1 0 ain5Cain6 0 1 1 1 ain7Cain8 0 1 1 0 9Cain10 (lfcsp package only; not a valid selection on the mqfp package) 1 ain 3, 2, 1, 0 ch3, ch2, ch1, ch0 1 1 1 1 aincomCaincom note that because the reference-detect does not operate on the refin2 pair, the refin2 pins can go below 1 v.
aduc845/aduc847/aduc848 rev. b | page 45 of 108 nly) lar or bipolar coding. the auxiliary adc is he a 45. t addressable: no . ad sfr bit d no. name adc1con (auxiliary adc control register) (aduc845 o adc1con is used to configure the auxiliary adc for reference, channel selection, and unipo available only on t duc8 sfr address: d3h power-on default: 00h bi table 27 c1con esignations bit description 7 CC write dont care. C not implemented. 6 axref le the auxiliary adc to use the internal band gap reference. he refin2 reference inputs. auxiliary (aduc845 only) adc external reference bit. set by the user to enable the auxiliary adc to use the external reference via refin. cleared by the user to enab auxiliary adc cannot use t 5 au lar bit. ing, that is, zero input results in 000000h output. o enable bipolar co ding, zero input results in 800000h output. ni auxiliary (aduc845 only) adc unipo set by the user to enable unipolar cod cleared by the user t 4 CC rite dont care. C not implemented. w auxiliary adc channel select bits. written by the user to select the auxiliary adc channel. ach3 ach2 ach1 ach0 selected auxiliary adc input range (v = 2.5 v). ref 0 0 0 0 ain1Caincom 0 0 0 1 ain2Caincom 0 0 1 0 ain3Caincom 0 0 1 1 ain4Caincom 0 1 0 0 ain5Caincom 0 1 0 1 ain6Caincom 0 1 1 0 ain7Caincom 0 1 1 1 ain8Caincom 1 0 0 0 ain9Caincom (not a valid selection on the mqfp package) 1 0 0 1 ain10Caincom (not a valid selection on the mqfp package) 1 0 1 0 ain1Cain2 1 0 1 1 ain3Cain4 1 1 0 0 ain5Cain6 1 1 0 1 ain7Cain8 1 1 1 0 temperature sensor 1 3, 2, 1, 0 ach3, ach2, ach1, ach0 1 1 1 1 aincomCaincom 1 note the following about the temperature sensor: when the temperature sensor is selected, user code must select the internal reference via the axref bit and clear the auni bit (adc1con.5) to select bipolar coding. chop mode must be enabled for correct temperature sensor operation. the temperature sensor is factory ca librated to yield conversion resu lts 800000h at 0c (adc chop on). a +1c change in temperature results in a +1 lsb change in the adc1h register adc conversion result. the temperature sensor is not avail able on the aduc847 or aduc848.
aduc845/aduc847/aduc848 rev. b | page 46 of 108 r th e ad c , a n sf r b i t d e s i g n at i o n s sf .7 sf .6 sf .5 sf .4 sf . s f .0 sf ( a dc sinc fil t er c o ntrol register) the s f r e g i s t er is us e d t o co nf i g ur e t h e de cima t i o n fac t o r fo s f r a ddr ess: d4h p o w e r - o n def a u l t: 45h d t h er efo r e , has a di r e c t inf l uen c e on t h e a d c t h r o ug hp u t r a t e . 3 s f .2 sf . 1 bi t a d dress a bl e: n o t a b l e 2 8 . si n c f i l t e r 0 1 0 0 0 1 0 1 t h e b i t s in th is r e gi s t e r se t th e d e ci ma ti o n fa ct o r o f th e a d c. t h i s h a s a d chop s e t t i n g . t h e e q u a t i ons u s e d to de te r m i n e t h e a d c t h rou g h p ut r a te a fa d c ( c h o p o n i r e c t bea r i n g o n th e th r o ugh p u t ra t e o f th e a d c alo ng w i t h t h e r e ) = sfword 8 3 1 32.768 kh z w h er e sfw o r d is in decima l . fa d c ( c h o p o f f ) = sfword 8 1 32.768 kh z w h er e sfw o r d is in decima l . t a b l e 2 9 . sf sf r b i t e x a m p l e s cho p enabled ( adcmo de.3 = 0) sf (decimal) sf (he x a d ecim al) f a dc (hz) t a dc (ms) t s ettle ( m s ) 13 1 0d 105.3 9 . 5 2 1 9 . 0 4 69 45 19.79 5 0 . 5 3 1 0 1 . 1 82 52 16.65 6 0 . 0 6 1 2 0 . 1 255 ff 5.35 1 8 6 . 7 7 3 7 3 . 5 4 cho p d isabled ( adcmo de.3 = 1) sf (decimal) sf (he x a d ecim al) f a dc (hz) t a dc (ms) t s ettle ( m s ) 3 03 1365.3 0 . 7 3 2 . 2 69 45 59.36 1 6 . 8 4 5 0 . 5 2 82 52 49.95 2 0 . 0 2 6 0 . 0 6 255 ff 16.06 6 2 . 2 5 1 8 6 . 8 1 w i t h ch op en a b led , i f a n sf w o r d sm a l l e r t h a n 13 i s w r i t t e n t o t h i s sf r e g dur i n g ad c ca li b r a t io n, t h e us er -p r o g r a m m e d val u e o f s f w o r did on p r e v io u i st er , t h e fi lt er a u d is us ed . s micr o c on ver t e r ? p r o d uc ts. h o we ver , fo r op t i m u m c a l i b r a t t . t o m a t i ca lly de fa ult s t o 13. th e s f w o r d do es n o t defa u l t t o t h e maxim u m s e t t in g (255) a s i t i o n r e s u l t s , i t i s r e comme n de d t h a t t h e maxi m u m sf wo r d be s e
aduc845/aduc847/aduc848 rev. b | page 47 of 108 icon (excitation current sources control registe the icon reg ources and the burno r) ut detection source. ister is used to configure the current s sfr address: d5h power-on default: 00h bit addressable: no table 30. excitation current source sfr bit designations bit no. name description 7 CCC not implemented. write do nt care. 6 icon.6 burnout current enable bit. when set, this bit enables the s ain7/ain8. not available on a ensor burn ny other ad out current sources on primary adc channels ain5/ain6 or c input pins or on the auxiliary adc (aduc845 only). 5 icon.5 not implemented. write don t care. 4 icon.4 not implemented. write dont care. 3 icon.3 iexc2 pin select. 0 selects ain8, 1 selects ain7 2 icon.2 iexc1 pin select. 0 selects ain7, 1 selects a in8 1 icon.1 iexc2 enable bit (0 = disable). 0 icon.0 iexc1 enable bit (0 = disa ble). a write to the icon register has an immediate effect but does n is already converting, the user must wait until the third or f ot reset th s e n adc ourth output a ast ( endi on t statu settled new output. both iexc1 and iexc2 can be configured to operate on the same output her y inc sing e cur to 40 0 a. e adc . ther fore, if a curren t source is changed whi le a t le dep ng he s of the chop mode) to see a fully pin t eb rea th rent source capability
aduc845/aduc847/aduc848 rev. b | page 48 of 108 , nonv ol a t ile fl ash/ee memor y overvie w the adu c 845/aduc847/adu c 848 in co r p o r a t e flas h/ee me m o r y t e chnolog y on- c hi p to p r o v ide t h e u s er wi t h non v ol a t i l e in-c ir c u i t r e p r o g r a mma b l e co d e a nd da t a m e mo r y sp ace. l i ke e e p rom , f l a s h me mor y c a n b e pro g r a m m e d i n - s y s te m a t th e b y te leve l , al th o u g h i t m u st f i rs t be eras e d , in p a g e b l o c ks. t h u s , f l a s h me mor y i s of te n a n d more c o r r e c t l y re fe r r e d to a s f l a s h / e e me mo r y . eeprom technology eprom technology f l a s h / e e m e m o technology in-circuit reprogrammable r y s pace efficient / density 04741-026 f i g u re 26. f l as h/e e m e m o r y d e vel o p m ent o v eral l , flash/e e m e m o r y r e p r es en ts a s t ep clos er t o t h e ide a l m e m o r y d e v i ce th a t in cl ud e s n o n v o l a t ili t y , i n - c ir cui t p r ogra m - ma b i l i ty , hig h den s i t y , an d lo w cos t . th e f l ash/ee m e m o r y t e chn o log y al lo ws t h e us er t o up da te p r og ra m co de s p ac e i n - cir c ui t, w i t h o u t n e e d ing t o r e place o n e t i m e p r og ra mma b l e (o t p ) devices a t r e m o te o p era t in g no des. f l a s h/ ee memo r y on th e a d u c 8 45, a d uc 84 7, a d u c 8 4 8 the adu c 845/aduc847/adu c 848 p r o v ide tw o a r ra ys o f f l a s h / e e me mo r y for u s e r a p pl i c a t i o n s u p to 6 2 kb y t e s of flash / ee p r og ra m sp ace and 4 k b y t es o f flash/ ee da t a m e m o r y s p ace . als o , 8- k b yt e and 32- k b y t e p r og ra m m e m o r y o p t i o n r e a 6 2 - kb y t e opt i on ; ho w e ve r , s i m i l proto c ol s and pro c e d u r e s are a p plic a b le t o t h e 32- k b yte an d 8-k b yt e op t i o n s unles s o t h e r w i s e n o t e d , p r o v i d e d t h a t t h e dif f er en ce in m e m o r y size is t a k e n i n to the 62 k b yt e s flash/ee co de s p ace a r e p r o v ide d o n -chi p t o faci li t a te co de e x e c u t io n w i t h ou t a n y ex ter n a l dis c r e te ro m d r d pa r t y m e m o r y p r ogra m m e r s, o r v i a a n y o ad) m o de. d in a d mo de . f o r t h e h e ul o a d a r e a t a k e s u p t h e to p 6 k b yt es o f t h e e a b le 62 k b yt es to 64 k b yt es. d en t , n s t a b l e , t h e a d uc845/aduc847/ aduc848 flas h/ee m e m o r y end u ran c e q u al if ica t ion has been o v er a n d e l es , wi th an end u rance f i gur e o f 700,00 0 c y c l es bein g typ i cal o f o p era t io n a t 25c. reten t ion is t h e a b i l i t y o f t h e fl ash/ee m e m o r y t o r e t a in i t s p r ogra mm e d da ta o v e r t i m e . a g a i n, t h e pa r t s ha v e b een q u ali f ie d i n a c co r d a n ce w i th th e f o rm al jed e c r e t e n t i o n l i f e ti m e s p ec i f i - ca tion (a117) a t a s p ec if ic j u nc tio n t e m p er a t ure (t j = 55c). a s p a r t o f t h is q u a l if ica t ion p r o c e d ur e , t h e flash/e e m e m o r y is c y cle d to i t s sp e c if ie d e n d u r a nc e lim i t de s c r i b e d p r e v io usly , b e fo r e d a t a r e t e n t io n is ch a r ac ter i ze d . t h is m e a n s t h a t t h e f l a s h / e e me mo r y i s g u ar an te e d to re t a i n i t s d a t a for i t s full sp e c if i e d r e te n t i o n l i fet i me e v er y t i me t h e f l a s h / ee m e mo r y i s r e p r og ra mm ed . i t s h o u l d als o b e n o t e d tha t r e ten t ion lif e time , b a s e d on an ac t i va t i on e n erg y o f 0.6 e v , der a t e s w i t h t j as sho w n in f i gur e 27. s a v a i la b l e . al l exa m ples an d r e fer e n c es i n t h is da t a sh e e t us e t h e a r acco un t. e vi ce r e q u ir e m en ts . the p r og ram me mo r y c a n b e p r o g ramme d in-c ir c u i t , usin g t h e s e r i a l do w n lo ad m o de p r o v ide d , usin g co n v en ti o n al t h i us er -def in ed p r o t o c ol in us er do wnlo ad (ul the 4- k b yt e f l as h/ee da t a me m o r y s p ace can b e us e d as a ge ne r a l - pu r p o s e, no n v o l a t i l e s c r a tch p a d are a . u s e r a c c e ss to t h i s a r e a is v i a a g r o u p o f s e ve n sfrs . th is sp ac e can b e p r og ra mm ed a t a b y te leve l , al tho u g h i t m u s t f i rs t b e eras e 4-b y te p a g e s. al l t h e fol l o w i n g s e c t io n s us e t h e 62- k b yte p r og ra m s p ace as an exa m ple w h e n r e fer r in g t o p r ogra m a nd ul o 64-k b yt e p a r t , t p r og ra m s p ace , tha t is, f r o m 56 k b yt es t o 62 k b yt es. f o r th e 3 2 - kb y t e p a r t , t h e ulo a d sp ac e mo v e s t o t h e to p 8 k b y t es o f t h o n - c h i p p r o g r a m m e m o r y , tha t is., f r o m 24 k b y t es t o 32 k b yt es. n o ulo a d mo de is a v a i l a ble on t h e 8 - k b y t e p a r t si nc e t h e boo t l o a d a r e a o n t h e 8- k b yt e p a r t is 8 k b yt es lon g , s o n o us us er p r og ra m sp ace r e ma in s. th e k e r n e l s t il l r e sides in t h e p r o t ec t e d a r e a f r o m f l ash/ee memor y r e lia bilit y t h e flas h/ ee p r ogra m a n d da t a m e m o r y a r ra y s o n t h e aduc845/adu c 847/adu c 84 8 a r e f u l l y q u alif ied f o r tw o k e y f l a s h / e e me mo r y ch ar a c te r i st i c s : f l a s h / e e me mor y c y cl i n g end u r a n c e and f l ash / ee m e m o r y da t a r e ten t io n. end u ran c e quan t i f i es t h e ab i l i t y o f t h e flas h/ee m e m o r y t o b e c y cle d t h r o ug h ma n y p r og ra m, r e ad , an d eras e c y cles. i n r e al t e r m s, a sin g le en d u ra n c e c y c l e is c o m p ose d o f fo u r in de p e n seq u e n t i al ev en ts : 1. i n i t i a l p a g e eras e s e q u e n ce 2. re ad/v er if y s e quen ce 3. by te p r o g r a m s e q u enc e 4. s e co nd r e ad/v er if y s e q u en ce i n r e l i a b i l i t y q u a l if ica t io n, e v er y b y t e i n b o t h t h e p r og ra m an d da ta f l ash/ee m e m o r y is c y c l ed f r o m 00h t o ffh un til a f i rs t f a i l i s re c o rd e d , s i g n i f y i ng t h e e n d u r a nc e l i m i t of t h e on - c h i p f l a s h / e e me mo r y . a s in d i ca t e d in t h e s p e c i f ica t io ca r r ied o u t in acco r d an ce wi th jed e c s p ecif ic a t io n a 1 1 7 t h e in d u s t r i al t e m p era t ur e ra n g e o f C40c, +25 c , + 8 5 c , +125c. (th e l f cs p p a c k a g e is q u al if ied t o +8 5c o n l y .) th e r e su l t s a l lo w t h e sp e c if ic a t ion o f a min i m u m e n d u ran c e f i gur o v er su p p l y and t e m p er a t ur e o f 1 00,0 00 c y c
aduc845/aduc847/aduc848 rev. b | page 49 of 108 40 60 70 90 t j junction temperature ( c) re te ntion (years) 250 200 150 100 50 0 50 80 110 300 100 adi specification 100 years min. at t j = 55 c 04741-028 f i gure 27. f l ash/ee memor y d a ta rete ntion l ash/ee progr a m memor y yt e a r ra y o f g r a m r o g r a m v a i l a n v da 2 k b yt e co n t a i n pe rm a n e n s e r i a l do wn lo a d , s em u l a t io n. th es e 2 k b yt es o f e m b e dde d f i r m w a r e als o co n t a i n e r - o n co n f i g t i n e t h a t do wn lo a d s fac t o r y ca li- f i cie n t as ad c, te m p er a re f e re nc e s . th e s e 2 k b yt es o f a r e hidden f r o m t h e us e r o de d f i r m wa r e a p p r co de. a t i r o b l o c k is us e d t o s t f the adu c 845/aduc847/ad u c 848 co n t ain a 64-k b f l a s h / ee p r o me mor y are a m e mo r y . t h e lo w e r 62 k b y t es o f t h is p b l e to t h e u s e r for p r o g r a m stor age or a s t a m e m o r y . a d di ti o n a l t h e u p p e r s o f this flash/ee p r ogra m m e m o r y a r ra y tl y em bedd ed f i rm w a r e , all o wi n g in - c i r cui t e r i a l deb u g, and n o ni n t r u si ve sin g le-pin a p o w u r a t io n r o u b r a t e d co e f s t o t h e va r i ous calib r a t e d p e r i ph erals s u ch t ur e s e n s o r , c u r r en t s o ur ces, b a nd ga p , and e m b e dde d f i r m w a r e co de . a t t e m p ts t r e ad t h is s p ace r e ad 0s; t h er e f o r e , t h e e m b e d- e a r s as n o p i n st r u c t io n s to us e i n n o r m al o p er n g mo de (p o w er -o n defa u l t), t h e 62 k b yt es o f us er flash / e e p g ra m m e m o r y a p p e a r as a si n g le b l o c k. this o r e t h e us er c o de as sh o w n in f i gur e 28. e m b e d d p e r m a n e n t e d l y c o d e t o b e d o f e l i n s t r u 62 kbytes of flash/ee program memory are available to the user. all of this space can be programmed from the permanently embedded download/debug kernel or in parallel programming mode d o w n l o a d / d e b u g k e r n e l e m b e d d e d f i r m w a r e a l l o w s o w n l o a d e d t o a n y o f t h e 6 2 k b y t e s t h e k e r n o n - c h i p p r o g r a m m e m o r y . p r o g r a m a p p e a r s a s n o p c t i o n s t o u s e r c o d e . . user program memory ffffh f7ffh 62kbyte 0000h 2kbyte f800h 04741-029 f i g u re 28. f l as h/e e p r og r a m m e m o r y m a p i n n o r m a l m o de i n nor m a l mo d e , t h e 6 2 kb y t e s of f l a s h / e e pro g r a m me mor y ca n b e p r o g r a m m e d b y s e r i a l d o w n lo adi n g and b y p a r a l l el p r o g ra mmin g . s e r i a l the adu c 845/aduc847/ad u c 848 facili ta te c o de do wnlo ad v i a t h e s t anda rd u a r t s e r i al p o r t . the p a r t s en ter s e r i al d o w n - lo a d mo d e a f t e r a r e s e t o r a p o wer c y cl e if t h e ps e n d o wnloa d ing (in- circ uit progr a mmin g) pi n i s pu l l e d lo w t h r o ug h an ext e r n a l 1 k? r e sist o r . on c e i n s e r i a l d o wn lo ad m o d e , t h e h i dden em bedd ed do wnlo a d k e r n e l ex ecu t es. t h i s allo ws t h e us e r t o do wnl o ad co de t o t h e ful l 62 k b yt es o f fl as h / ee p r og ra m m e m o r y w h ile t h e de v i ce is i n cir c ui t i n i t s t a rg et ap p l i c at i o n h a r d w a r e . a p c s e r i a l d o w n l o a d e x e c ut abl e ( w sd . e x e ) i s prov i d e d a s p a r t o f th e adu c 845/adu c 84 7/aduc848 q u ic k s t a r t deve lo p m en t sys t em. a p p l ic a t io n n o te uc004 f u l l y des c r i bes t h e s e r i a l do w n l o ad p r o t o c ol t h a t is us e d b y t h e em b e dde d d o w n l o a d k e r n e l . t h i s ap p l i c at i o n n o t e i s av a i l a b l e at ww w . a n a l o g . c o m / m i c r o c o n v e r t e r . p a r a llel pro g ra mming t h e de is f u ll y co m p a t i b le wi t h co n v t y f l as h o r eep r o m d e vice p r og ra mm er s . a b r e q u ir e d to supp mo t e r f ace , and p1.0 o p era t e s as t gen a t io n p o r t s t h a t co nf igur e t h e de vice fo r va r i ous pro r a s e op e r a t i o ns du r i ng p a r a l l el pro g r a m m i ng . p a ralle l p r ogra mmin g m o en t i o n al t h ir d- pa r l o c k d i a g r a m o f t h e ex ter n a l p i n conf igur a t io n or t p a r a l l el pro g r a m m i ng i s sh ow n i n fi g u re 2 9 . i n t h i s de, p o r t s 0 and 2 op er a t e as t h e exter n al addres s b u s i n t e r f ace, o p era t es as t h e ext e r n al da t a b u s in p 3 h e wr i t e enab le s t r o b e . p1.1, p1.2, p1.3, a nd p1.4 a r e us e d as e r a l co nf igu r g r a m and e p1.4 ?p1.1 p3.7 ?p3.0 ea reset a d u c +5v 8 4 5 / aduc847/ aduc848 c ommand p1.7 ?p1.5 timing data 04741-030 gnd v dd enable p1.0 the co p 1 . t a b f i g u re 29. f l as h/e e m e m o r y p a r a ll el p r og r a m m i n g mmand w o r d s t h a t a r e as sig n e d t o p1.1, p1.2, p1.3, an d 4 a r e des c r i b e d i n t a b l e 31. l e 31. fl ash/ee m e mor y p a r a l l e l p r og r a mmin g m o des po r t 1 p i n s p1.4 p1.3 p1.2 p1.1 p r ogr a mming mode 0 0 0 0 er ase f l ash/ee p r og r a m, da ta , and se c u ri ty mo de 1 0 1 0 p r og r a m c o de b y te 0 0 1 0 p r og r a m da ta b y te 1 0 1 1 r e ad c o de byte 0 0 1 1 r e ad da ta byte 1 1 0 0 p r og r a m s e cur i t y m o des 1 1 0 1 r e ad/v er ify s e cur i t y m o des all other c o d e s r e d u nd an t
aduc845/aduc847/aduc848 rev. b | page 50 of 108 d e . w r y c a n a l s o b e t . a n e f i gur e 30. ulo a d m o de can b e us ed t o u p g r ade t h e co de in l o ad p r o t ocol . b y co n f i g urin g v e , i t , o de can b e us ed t o s a ve da t a t o t h e n b e ext r eme l y us ef u l in f t h e 62 k b yt es o f flas h/ee p r og ra m m e a n s r e , i t r a s e d or re pro g r a m m e d b y e r rone ou s r i n g t h e f l ash/ee p r o g ra m m e m o r y v i a ulo a d t h r y c o n t r o l s f r d n o t e uc007 u s e r d o w n lo a d m o d e ( u lo a d ) f i gur e 28 sh o w s tha t i t is p o s s i b l e t o us e t h e 62 k b yt es o f flash / ee p r og ra m m e m o r y a v ai la b l e t o t h e us e r as o n e sing le bl o c k of me mor y . i n t h i s mo d e , a l l t h e f l a s h / e e me mor y i s re a d - o n l y to u s e r c o h o e ve r , mo st of t h e f l a s h / e e pro g r a m me m o wr i t e n to d u r i ng r u n t i m e si m p ly b y en ter i n g u l o a d m o d e i n u l o a d mo d e , t h e l o w e r 5 6 kb y t e s of pro g ram me mor y c b e r a s e d and r e p r og ra mm e d b y t h e us er s o f t w a r e as s h o w n i n t h e f i e l d via a n y use r -d e f in ed do w n th e s p i p o r t o n th e aduc845 /aduc847/adu c 8 4 8 a s a s l a is p o s s i b le t o co m p lete l y r e p r ogra m t h e 56 k b ytes o f flas h/ee p r og ra m m e m o r y in un der 5 s (s ee a p p l ic a t ion n o t e u c 0 0 7 user download mode at www. a n a l og . c o m / microconverter ). alternatively, uload m 56 k b yt es o f flas h/ee m e m o r y . t h i s c a d a t a log g i ng a pplica t ion s w h ere t h e p a r t s ca n p r o v id e u p t o 60 k b y t es o f da t a me m o r y o n -chi p (4 k b y t es o f de di ca te d f l a s h / e e d a t a me mor y a l s o e x i s t ) . the u p p e r 6 k b yt es o m e m o r y (8 k b ytes o n t h e 32- k b yt e p a r t s) a r e p r og ra mma b l e o n ly vi a s e r i a l d o w n lo ad o r p a ra l l el p r og ra mmi n g . t h i s e ad- o nl y t o us er co de; t h er efo t h a t t h is s p ace a p p e a r s as r c a n n ot b e a c c i d e n t a l ly e co de exe c u t ion, makin g i t v e r y s u i t ab le t o us e t h e 6 k b yt es as a b o ot l o a d e r . a b o ot l o a d e n abl e opt i on e x i s t s i n t h e w i n d o w s ? s e r i al do wnlo ader (w s d ) t o a lwa y s r u n f r o m e000h a f t e r res e t. i f usin g a b o ot lo ader , t h is o p t i o n is r e commende d t o en s u r e t h a t t h e b o o t lo ader alwa ys exe c u t es co r r e c t co d e a f t e re s e t . pr o g ra m m m o de is de s c r i b e d i n e f l a s h / ee m e m o s e c t io n o f econ an a l s o in a p p l ica t io n (w w w . a nalog.com/micr o c o n ver t er). embedded download/debug kernel permanently embedded firmware allows code to be downloaded to any of the 62 kbytes of on-chip program memory. the kernel program appears as nop instructions to user code. user bootloader space the user bootloader space can be programmed in download/debug mode via the kernel but is read only when executing user code user downloader space either the dow nload/debug kernel or user code (in c a n p r o g r a m u l o a d m o d e ) this space ffffh 2kbyte f 8 f7ffh 6kbyte e000h dfffh 0 0 h 56kbyte 0000h 04741-031 f i g u re 30. f l as h/e e p r og r a m m e m o r y m a p i n u l oa d m o de (6 2-k b y t e p a r t ) s t a r tin g a t 6000 h. th e m e m o r y ma p p i n g is sh o w n in f i gur e 31 . 62 kbytes of user code memory the 32- k b yt e mem o r y p a r t s ha v e t h e us er b o ot lo ad s p ace embedded download/debug kernel permanently embedded firmware allows code to be downloaded to any of the 32 kbytes of on-chip program memory. the kernel program appears as nop instructions to user code. user bootloader space the user bootloader space can be programmed in download/debug mode via the kernel but is read only when executing user code user downloader space either the dow nload/debug kernel or user code (in uload mode) can program this space not available to user ffffh 2kbyte f800h 8000h 8kbyte 6000h 5fffh 24kbyte 0000h 04741-074 32 kbytes of user code memory f i g u re 31. f l as h/e e p r og r a m m e m o r y m a p i n u l oa d m o de (3 2-k b y t e p a r t ) ul o a d m o de i s n o t a v ai lab l e on t h e 8- k b yt e f l as h/ee p r og ra m me mor y p a r t s . f l a s h/ ee pro g ra m mem o r y s e curi t y the adu c 845/aduc847/ad u c 848 facili ta te t h r e e m o des o f f l a s h / e e pro g r a m me mor y s e c u r i t y : t h e l o c k , s e c u re, an d s e r i a l s a fe m o de s. t h e s e m o des ca n b e i n de p e n d e n t l y ac t i va te d, r e st r i c t in g acce ss t o t h e in t e r n a l co de sp ac e . t h e y ca n b e ena b le d as p a r t o f s e r i a l d o wn lo ad p r o t o c ol, as des c r i b e d i n a p p l ica t io n n o te uc004, o r via p a ral l e l p r og ra mming. lo c k m o d e this m o d e lo ck s t h e co de me mo r y , dis a b l in g p a ra l l el p r o g ra m- m i ng of t h e pro g r a m me mor y . h o we ve r , re a d i n g t h e me mor y i n p a r a l l el m o de and r e ad in g t h e m e m o r y v i a a mo v c co mmand f r o m exter n al me m o r y a r e s t i l l a l lo we d . thi s mo de is de ac t i va te d b y in i t ia t i n g an er as e c o de and d a t a co mman d in s e r i a l d o wnlo ad o r p a ralle l p r ogra mmin g m o d e s. sec u r e mod e this m o d e lo ck s t h e co de me mo r y , dis a b l in g p a ra l l el p r o g ra m- m i ng of t h e pro g r a m me mor y . r e a d i n g / ve r i f y i n g t h e me mor y in p a ra l l e l m o d e a nd r e a d in g t h e in t e r n a l m e m o r y v i a a mo v c co mman d f r o m ex ter n a l me m o r y a r e a l s o dis a b l e d . this mo de is de ac t i va te d b y ini t ia t i n g an e r as e c o de and d a t a co mman d in s e r i a l d o w n lo ad or p a ra l l el p r o g ra mming m o des. se r i a l s a f e m o d e this m o de dis a b l es s e r i al do wn lo ad ca p a b i li ty o n t h e de vice . i f s e r i a l s a fe m o de is ac t i va te d and a n a t te m p t is m a de to r e s e t t h e p a rt i n t o s e ri a l d o w n l o a d m o d e , t h a t i s , r e s e t a s s e rt ed ( p u l l e d hig h ) and de -ass er te d (p u l le d l o w) w i t h ps en lo w , t h e p a r t in t e r p r e ts t h e s e r i a l d o w n lo ad res e t as a n o r m a l r e s e t o n ly . i t t h e r e f o r e does n o t en t e r se r i al do wnl o ad m o de , b u t e x ec u t e s o n l y a n o rm a l r e se t se q u e n c e . se ri a l s a f e m o d e c a n be d i s a b l ed o n l y b y in i t ia t i n g an er as e c o de and d a t a co mman d in p a ralle l p r ogra mmin g m o d e .
aduc845/aduc847/aduc848 rev. b | page 51 of 108 using fl as h/ee d a t a memor y the 4 k b yt es o f flas h/ee da t a m e m o r y a r e co nf igur ed as 102 4 p a g e s, eac h o f 4 b y t e s. a s wi th t h e o t h e r aduc845/aduc847 / aduc848 p e r i p h erals, t h e in t e r f ace t o this m e m o r y s p ace is via a g r oup of re g i ste r s m a pp e d i n t h e sf r sp a c e. a g r oup of f o u r da ta r e g i s t ers (e d a t a 1C4) h o lds th e 4 b y t e s o f da ta a t ea ch p a ge. t h e p a ge i s addr ess e d v i a t h e e a drh and eadrl re g i ste r s . f i n a l l y , e c on i s an 8 - bit c o n t ro l re g i s t e r t h a t c a n b e wr i tte n to w i t h o n e o f ni ne f l a s h / ee me mo r y a cce ss comm and s t o t r ig ger va r i o u s r e ad , wr i t e, e r as e, an d ver i f y f u n c t i o n s. a b l o c k di a g r a m of t h e s f r i n t e r f ace t o t h e f l ash/e e da t a me mo r y a r ra y is s h o w n in f i gur e 32. ec onf lash/ee memor y control sfr p r og ra mmin g ei t h er flash/ee da ta m e m o r y o r flas h/ee pro g r a m me mo r y i s d o ne t h rou g h t h e f l a s h / e e me mor y c o n t ro l sf r ( e c o n ) . t h i s sf r a l l o w s t h e u s e r to re a d , w r ite, eras e , o r v e r i f y th e 4 k b yt es o f fl as h/ee da t a m e m o r y o r th e 5 6 kb y t e s of f l a s h / e e pro g r a m me mor y . byte 1 (0000h) e data1 s f r byte 1 (0004h) byte 1 (0008h) byte 1 (000ch) byte 1 (0ff8h) byte 1 (0ffch) byte 2 (0001h) e data2 s f r byte 2 (0005h) byte 2 (0009h) byte 2 (000dh) byte 2 (0ff9h) byte 2 (0ffdh) byte 3 (0002h) e data3 s f r byte 3 (0006h) byte 3 (000ah) byte 3 (000eh) byte 3 (0ffah) byte 3 (0ffeh) byte 4 (0003h) e data4 s f r byte 4 (0007h) byte 4 (000bh) byte 4 (000fh) byte 4 (0ffbh) (0fffh) 01h 00h 02h 03h 3feh 3ffh p a ge addre s s (e adrh/l) byte addresses are g i v e n i n brackets 04741-032 byte 4 f i gure 32. f l ash/ee d a t a me mor y c o ntr o l and configu r ation t a bl e 32. ec o n fl a s h/ee m e mo r y c o mmands ec on v a l u e c o mmand des c ription (normal mode , p o w e r- o n default) c o mmand des c ription (ul o ad mo de) 01h r e ad 4 b ytes in the f l ash/ ee d a t a memor y , add r essed by the pag e addr ess ea drh/l , ar e r e ad in to ed a t a1C4 . not implemen t ed . u s e the mo vc instruc t ion. 02h w r ite r e sults in 4 b y tes in ed a t a1C4 b e ing wr itten to the f l ash/ee da ta memor y , a t the page addr ess g i v e n b y eadrh (0 ead rh < 0400h). note tha t the 4 b y tes in the page being addr ess e d must be pr e - erased . bytes 0 to 255 o f in ter n al xr a m ar e wr itten to the 256 b y tes of f l a s h/ee pr ogr a m memor y a t the page addr ess giv e n b y eadrh/l (0 e a drh/l < e0h). note tha t the 256 b y tes in the page being ad d r e ssed must be pr e - erased . 0 3 h re s e r v e d . re s e r v e d . 04h v e r i f y v e rifies tha t the da ta in ed a t a1C 4 is c o n t ained in the page addr ess g i v e n b y eadrh/l. a subsequen t r e ad of the ec on sfr r e sults in a 0 being r e ad if the v e rifica tion is v a lid , or a no n z er o v a lue bei n g r e ad to indica te an in v a lid v e r i fica ti on. not implemen t ed . u s e the mo vc and movx in struc t ions to v e r i fy the w r ite i n sof t w a r e . 05h er ase p a ge 4-b y t e page of f l ash/ee da ta memor y addr ess is er ased b y the page add r ess eadrh/l. 64-b y t e page of flash/ee pr og ram memor y addr essed b y the b y t e addr ess eadrh/l is er ased . a new page star ts when eadrl is equal to 00h, 80h, or c0h. 06h er ase all 4 k b yt es of f l ash/ee da ta memor y ar e er ased . the en tir e 56 k b ytes of ul o a d ar e er a s ed . 81h r e adbyte t h e b y t e in the f l as h/ ee da ta memor y , addr es s e d b y the b y t e addr ess eadrh/l, is r e ad int o ed a t a1 (0 e a drh/l 0fffh). not implemen t ed . u s e the mo vc c o mmand . 82h w r itebyte the b y t e in ed a t a1 is writt e n in t o f l ash/ee da ta memor y a t the b y t e addr ess eadrh/l. the b y te in ed a t a1 is wr itten in to f l ash/ee pr ogr a m memor y a t the b y t e addr ess eadrh/l (0 eadrh/l dff f h). 0fh exul o a d c o nfigur es the ec on instruc t ions (abov e) to op er a t e on f l ash/ee da ta memor y . en t e rs normal mode , dir e c t ing su bseque n t ec on instruc t ions to opera t e on the f l ash/ee da ta memor y . f0h ul o a d en ters ul o a d mode; subsequ e n t ec on instruc t ions opera te on f l as h/ee pr ogram m e mor y . enables the ec on instruc t ions t o opera t e on the f l ash/ee pr ogram memor y . ul o a d en tr y mode .
aduc845/aduc847/aduc848 rev. b | page 52 of 108 example: programming the flash/ee data memory a user wants to program f3h into the second byte on page 03h of the flash/ee data memory space while preserving the other 3 bytes already in this page. a typical program of the flash/ee data array involves 1. setting eadrh/l with the page address. 2. writing the data to be programmed to the edata1C4. 3. writing the econ sfr with the appropriate command. step 1: set up the page address address registers eadrh and eadrl hold the high byte address and the low byte address of the page to be addressed. the assembly language to set up the address may appear as mov eadrh, #0 ;set page address pointer mov eadrl, #03h step 2: set up the edata registers write the four values to be written into the page into the four sfrs edata1C4. unfortunately, the user does not know three of them. thus, the user must read the current page and overwrite the second byte. mov econ, #1 ;read page into edata1-4 mov edata2, #0f3h ;overwrite byte 2 step 3: program page a byte in the flash/ee array can be programmed only if it has previously been erased. specifically, a byte can be programmed only if it already holds the value ffh. because of the flash/ee architecture, this erasure must happen at a page level; therefore, a minimum of 4 bytes (1 page) are erased when an erase command is initiated. once the page is erased, the user can program the 4 bytes in-page and then perform a verification of the data. mov econ, #5 ;erase page mov econ, #2 ;write page mov econ, #4 ;verify page mov a, econ ;check if econ = 0 (ok!) although the 4 kbytes of flash/ee data memory are factory pre- erased, that is, byte locations set to ffh, it is good programming practice to include an eraseall routine as part of any configuration/set-up code running on the parts. an eraseall command consists of writing 06h to the econ sfr, which initiates an erase of the 4-kbyte flash/ee array. this command coded in 8051 assembly language would appear as mov econ, #06h ;erase all command ;2ms duration flash/ee memory timing typical program and erase times for the parts are as follows: normal mode (operating on flash/ee data memory) command bytes affected readpage 4 bytes 25 machine cycles writepage 4 bytes 380 s verifypage 4 bytes 25 machine cycles erasepage 4 bytes 2 ms eraseall 4 kbytes 2 ms readbyte 1 byte 10 machine cycles writebyte 1 byte 200 s uload mode (operating on flash/ee program memory) writepage 256 bytes 15 ms erasepage 64 bytes 2 ms eraseall 56 kbytes 2 ms writebyte 1 byte 200 s a given mode of operation is initiated as soon as the command word is written to the econ sfr. the core microcontroller operation is idled until the requested program/read or erase mode is completed. in practice, this means that even though the flash/ee memory mode of operation is typically initiated with a two-machine-cycle mov instruction (to write to the econ sfr), the next instruction is not executed until the flash/ee operation is complete. this means that the core cannot respond to interrupt requests until the flash/ee operation is complete, although the core peripheral functions such as counter/timers continue to count as configured throughout this period.
aduc845/aduc847/aduc848 rev. b | page 53 of 108 dac circuit information the aduc845/aduc847/ aduc848 incorporate a 12-bit, voltage output dac on-chip. it has a rail-to-rail voltage output buffer capable of driving 10 k?/100 pf, and has two selectable ranges, 0 v to v ref and 0 v to av dd . it can operate in 12-bit or 8-bit mode. the dac has a control register, daccon, and two data registers, dach/l. the dac output can be programmed to appear at pin 14 (dac) or pin 13 (aincom). in 12-bit mode, the dac voltage output is updated as soon as the dacl data sfr is written; therefore, the dac data registers should be updated as dach first, followed by dacl. the 12- bit dac data should be written into dach/l right-justified such that dacl contains the lower 8 bits, and the lower nibble of dach contains the upper 4 bits. daccon control register sfr address: fdh power-on default: 00h bit addressable: no table 33. daccondac configuration commands bit no. name description 7 CCC not implemented. write dont care. 6 CCC not implemented. write dont care. 5 CCC not implemented. write dont care. 4 dacpin dac output pin select. set to 1 by the user to direct the dac output to pin 13 (aincom). cleared to 0 by the user to direct the dac output to pin 14 (dac). 3 dac8 dac 8-bit mode bit. set to 1 by the user to enable 8-bit dac operation. in this mode, the 8 bits in dacl sfr are routed to the 8 msbs of the dac, and the 4 lsbs of the dac are set to 0. cleared to 0 by the user to enable 12-bit dac operation. in this mode, the 8 lsbs of the result are routed to dacl, and the upper 4 msb bits are routed to the lower 4 bits of dach. 2 dacrn dac output range bit. set to 1 by the user to configure the dac range of 0 v to av dd . cleared to 0 by the user to configure the dac range of 0 v to 2.5 v (v ref ). 1 dacclr dac clear bit. set to 1 by the user to enable normal dac operation. cleared to 0 by the user to reset the dac data registers dacl/h to 0. 0 dacen dac enable bit. set to 1 by the user to enable normal dac operation. cleared to 0 by the user to power down the dac. dach/dacl data registers these dac data registers are written to by the user to update the dac output. sfr address: dacl (dac data low byte)fbh dach (dac data high byte)fch power-on default: 00h (both registers) bit addressable: no (both registers)
aduc845/aduc847/aduc848 rev. b | page 54 of 108 using th e d a c t h e on - c h i p d a c arch ite c tu re c o ns i s t s of a re s i stor st r i ng d a c f o l l o w ed b y a n o u t p u t b u f f er a m p l if ier , t h e f u n c tio n al eq uival e n t o f w h ich is sh o w n i n f i gur e 33 . output buffer high-z disable (from mcu) r r r r r av dd v ref 04741-033 14 f i gur e 3 3 . resi st or str i ng d a c f u ncti ona l e q ui v a l e nt f e a t u r e s of t h i s arch i t e c t u re i n clu d e i n he re n t g u ar an te e d m o n o t o nici ty and exce l l en t dif f er en t i al li n e a r i t y . a s s h o w n in f i gur e 33, t h e refer e n c e s o ur ce fo r t h e d a c is us er -s e l e c t a b l e i n so ft w a r e . i t c a n be ei t h e r a v dd or v ref . i n 0 v - to-a v dd mo de, th e d a c o u t p u t tra n sf e r fun c ti o n s p a n s f r o m 0 v t o th e v o l t a g e at t h e a v dd p i n. i n 0 v - t o -v ref m o de , t h e d a c o u t p u t t r a n sfer fun c ti o n s p a n s f r o m 0 v t o th e in t e rn al v ref (2.5 v). th e d a c o u t p u t b u f f er a m p l if ier f e a t ur es a tr ue ra il-t o-r a il o u t p u t s t a g e i m p l em en ta ti o n . t h i s m e a n s tha t , unload ed , e a c h o u t p u t i s ca p a b l e o f s w ing i n g t o wi t h in l e s s tha n 100 mv o f bo t h a v dd a nd g r o u nd . m o r e o v er , t h e d a c s li n e a r i t y sp e c if ica t ion (w h e n dr i v in g a 10 k? r e sist i v e lo ad t o g r o u n d ) is gua r a n t e e d t h r o ug h th e f u l l tra n sf er f u n c tion excep t c o des 0 t o 48 in 0 v - t o -v ref m o de; c o des 0 t o 100; a nd c o des 3950 t o 4095 in 0 v - t o -v dd mo d e . l i n e a r i t y deg r a d a t io n ne a r g r o u nd an d v dd is ca us e d b y s a t u r a - t i on o f t h e out p u t am pl if ier ; a ge n e r a l r e p r e s e n t a t i on of i t s ef fe c t s ( n e g l e c t i n g of f s e t a n d g a i n e r ror ) i s show n i n fi g u re 3 4 . t h e do t t e d l i n e i ndi ca tes t h e id e a l t r a n sfer f u n c t i o n , a nd t h e s o li d line r e p r es en ts w h a t t h e t r a n sfer f u n c t i o n mig h t lo ok li k e wi t h en d p o i n t n o nlin ea r i t i es d u e t o s a t u ra tio n o f t h e o u t p u t a m p l i f i e r . o t e t h a t f i gure 34 r e p r es en ts a t r a n sfer f u n c t i o n in 0 - t o -v dd ref < v dd ), the lo w e r o u e r , b u t t h e u p p e r p o r t io n o f t h e u l w th e i d e a l lin e t o th e e n d , t h h - e n d e ndp oi n t l i n e ar it y e r ror . n mo d e on ly . i n 0 v - to - v ref mo d e ( w i t h v n o nl i n e a r i t y w l d b s i mi l a tra n sf e r fun c ti o n w o d f o l l o sh ow i n g no s i g n s of e h i g v dd ? 50mv v dd v dd ?100mv 100mv 50mv 0mv 000h fffh 04741- 034 f i gure 34. e n dpo i n t non lin ea riti es d u e to a m p lifi e r s a tu r a tio n the en d p o i n t no nlin ea r i t i es sho w n in f i gur e 3 4 becom e w o rs e as a f u n c t i o n o f o u t p ut lo ading. m o st d a t a sh e e t sp e c if ic a t io n s assu m e a 10 k? r e sist i v e lo ad t o g r o u n d a t t h e d a c o u t p ut. a s th e o u t p u t i s f o r c ed t o so u r ce o r s i nk m o r e cu rr en t , th e n o nl in ea r re g i ons a t t h e to p or b o tto m , re s p e c t i v e ly , of f i g u re 3 4 b e c o me la rg er . w i t h la rg er c u r r en t dema n d s, t h is can si g n if ica n t l y limi t o u t p u t v o l t a g e s w in g. f i gur e 35 a nd f i gur e 36 il l u s t ra t e this b e ha vio r . n o t e t h a t t h e up p e r t r ace i n e a ch o f t h es e f i gur e s is v a l i d on ly f o r an output r a nge s e l e c t i o n of 0 v to a v dd . i n 0 v - to - v ref m o de , d a c lo adin g do es n o t ca us e hi g h -si d e v o l t a g e n o nl i n e a r i t i es w h i l e t h e r e fer e n c e v o l t a g e r e mai n s b e lo w t h e u p p e r t r ace i n t h e co r r es p o ndi n g f i gur e . f o r exa m ple , if a v dd = 3 v a nd v ref = 2.5 v , t h e hig h -side v o l t a g e is n o t a f fe c t e d b y lo ads o f les s tha n 5 ma. b u t a r ound 7 ma, t h e u p p e r c u r v e in f i gur e 36 dr o p s be l o w 2.5 v (v ref ) , i n d i c a t i n g th a t a t th e s e hig h er c u r r en ts, t h e o u t p u t is no t ca p a b l e o f r e achin g v ref . source/sink current (ma) 5 0 5 10 15 output voltage (v) 4 3 2 1 0 dac loaded with 0000h dac loaded with 0fffh 04741-035 f i gure 35. s o urc e and sink curr ent capabilit y with v ref = a v dd = 5 v
aduc845/aduc847/aduc848 rev. b | page 55 of 108 source/sink current (ma) 3 0 5 10 15 output voltage (v) 2 1 0 dac loaded with 0000h dac loaded with 0fffh 04741-036 f i gure 36. s o urc e and sink curr ent capabilit y with v ref = a v dd = 3 v f o r la rg er l o ads, t h e c u r r e n t dr iv e ca p a b i l i ty ma y n o t b e s u f f i - cien t . t o i n cr e a s e t h e s o ur c e a nd sin k c u r r en t c a p a b i l i ty o f t h e d a c, an ext e r n al b u f f er s h o u ld be adde d as sho w n in f i gur e 3 7 . aduc845/ aduc847/ aduc848 dac 04741-037 14 f i gure 3 7 . bufferi ng the d a c o u tput the i n t e r n al d a c o u t p ut b u f f er als o fe a t ur es a hig h i m p e dance d i s a b l e fun c ti o n . i n th e c h i p s d e f a ul t po w e r - o n s t a t e , th e d a c is dis a b l e d an d i t s o u t p u t is i n a hig h im p e dan c e st a t e (o r t h r e e- st a t e) w h er e i t r e ma in s inac t i ve un t i l enab le d in s o f t wa r e . this m e an s tha t if a zer o o u t p u t is desir e d d u r i n g p o w e r - o n o r p o w e r - do wn t r an sien t condi t i on s, a p u l l - d o w n r e sisto r m u st b e adde d t o each d a c o u t p u t . a s sumin g t h a t t h is r e sis t o r is in pl a c e, t h e d a c output re m a i n s a t g r ou n d p o te n t i a l w h e n e v e r th e d a c i s d i sa b l ed . pulse- wid t h modul a t o r ( p wm) the adu c 845/aduc847/ad u c 848 has a hig h l y f l exi b le pwm o f fer i n g p r ogra mma b l e r e s o l u t i o n an d an i n p u t clo c k. t h e pwm can b e conf igur e d in s i x dif f er en t m o des o f o p er a t io n. t w o o f t h es e mo des al lo w t h e pwm t o b e co nf igur e d as a - ? d a c w i t h up to 1 6 bit s of re s o lut i on . a bl o c k d i ag r a m of t h e pwm is sh o w n in f i gur e 38. clock select programmable divider compare mode pwm0h/l pwm1h/l 12.583mhz (f vco) 32.768khz/15 32.768khz (f xtal) external clock on p2.7 p2.5 p2.6 16-bit pwm counter 04741- 038 f i gur e 3 8 . pw m bloc k dia g r a m the p w m us es co n t r o l s f r , p w mc on, and fo ur da t a s f rs: pwm0h, p w m0l, pwm1h, a nd pwm1 l. pwmc o n (as des c r i b e d in t a b l e 34) co n t r o ls t h e dif f er en t mo d e s of op e r a t i o n of t h e p w m a s wel l a s t h e p w m cl o c k f r e q u e nc y . pwm0h/l a n d pwm1h/l a r e t h e da t a r e gist ers t h a t d e t e rm i n e t h e d u ty c y cles o f t h e pwm o u t p u t s a t p2.5 and p2.6 . t o us e t h e pwm us er s o f t wa r e , f i rs t wr i t e t o p w mc o n t o s e le c t t h e p w m m o de o f o p er a t io n an d t h e pw m in p u t clo c k. w r i t i n g t o p w m c o n al so r e se t s t h e pw m c o u n t e r . i n a n y o f th e 16 -b i t m o des o f o p era t io n ( m o d es 1, 3, 4, 6 ) , us er s o f t wa r e s h o u l d wr i t e t o t h e pwm0l o r pwm1l s f rs f i rs t. this val u e is w r it te n to a h i d d e n sf r . w r i t i n g to t h e p w m 0 h or p w m 1 h sf r s up d a te s b o t h t h e p w m x h an d t h e p w m x l sf r s but d o e s n o t c h a n g e th e o u t p u t s u n ti l th e e n d o f th e pw m c y c l e i n p r og r e s s . th e v a l u es wr i t t e n t o t h es e 16- b i t r e g i s t ers a r e t h en us ed in t h e n e xt pwm c y c l e .
aduc845/aduc847/aduc848 rev. b | page 56 of 108 pwmcon pwm control sfr sfr address: aeh power-on default: 00h bit addressable: no table 34. pwmcon pwm control sfr bit no. name description 7 CCC not implemented. write dont care. pmw mode selection. pwm2 pwm1 pwm0 0 0 0 mode 0: pwm disabled. 0 0 1 mode 1: single 16-bit output with programmable pulse and cycle time. 0 1 0 mode 2: twin 8-bit outputs. 0 1 1 mode 3: twin 16-bit outputs. 1 0 0 mode 4: dual 16-bit pulse density outputs. 1 0 1 mode 5: dual 8-bit outputs. 1 1 0 mode 6: dual 16-bit pulse density rz outputs. 6, 5, 4 pwm2, pwm1, pwm0 1 1 1 mode 7: pwm counter re set with outputs not used. pwm clock source divider. pws1 pws0 0 0 selected clock. 0 1 selected clock divided by 4. 1 0 selected clock divided by 16. 3, 2 pws1, pws0 1 1 selected clock divided by 64. pwm clock source selection. pwc1 pwc0 0 0 f xtal /15 (2.184 khz). 0 1 f xtal (32.768 khz). 1 0 external input on p2.7. 1, 0 pwc1, pwc0 1 1 f vco (12.58 mhz). pwm pulse width high byte (pwm0h) sfr address: b2h power-on default: 00h bit addressable: no table 35. pwm0h: pwm pulse width high byte pwm0h.7 pwm0h.6 pwm0h.5 pwm0h.4 pwm0h.3 pwm0h.2 pwm0h.1 pwm0h.0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w pwm pulse width low byte (pwm0l) sfr address: b1h power-on default: 00h bit addressable: no table 36. pwm0l: pwm pulse width low byte pwm0l.7 pwm0l.6 pwm0l.5 pwm0l.4 pwm0l.3 pwm0l.2 pwm0l.1 pwm0l.0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w
aduc845/aduc847/aduc848 rev. b | page 57 of 108 pwm c y cle w i dth hi gh by t e ( p wm1h) s f r a ddr ess: b4h p o w e r - o n def a u l t: 00h bi t a d dress a bl e: n o t a ble 37. pw m1h: pwm cy cl e w i d t h h i g h b y t e pw m 1 h . 7 pw m 1 h . 6 pw m 1 h . 5 pw m 1 h . 4 pw m 1 h . 3 pw m 1 h . 2 pw m 1 h . 1 pw m 1 h . 0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w pwm c y cle w i dth l o w by t e (pwm1l) s f r a ddr ess: b3h p o w e r - o n def a u l t: 00h bi t a d dress a bl e: n o t a ble 38. pw m1l: pwm c y cl e w i d t h l o w b y t e pw m 1 l . 7 pw m 1 l . 6 pw m 1 l . 5 pw m 1 l . 4 pw m 1 l . 3 pw m 1 l . 2 pw m 1 l . 1 pw m 1 l . 0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w mo de 0 i n m o de 0, t h e pwm is dis a b l e d , a l lo wi n g p2.5 a nd p2.6 to b e us ed as n o r m al dig i tal i/o s . mo de 1 ( s ingle - v a ria b le r e sol u tion pwm) i n m o de 1, b o t h t h e p u ls e len g t h an d t h e c y cle t i m e (p er io d) a r e p r o g r a m m a b l e i n use r cod e , all o w i n g th e r e so l u ti o n o f th e pw m t o b e va r i ab l e . p w m 1 h / l s e ts t h e p e r i o d o f t h e o u t p ut w a v e fo r m . r e d u ci n g pw m1 h / l r e d u c e s th e r e so l u ti o n o f th e pw m o u t p u t b u t in cr e a s e s t h e max i m u m o u tp u t ra te o f t h e p w m. f o r exa m p l e , s e t t in g pwm1h / l t o 65536 g i v e s a 16 -b i t p w m wi t h a maxim u m o u t p u t ra t e o f 192 h z (12.583 m h z/65536). s e t t ing pwm1h / l t o 4 096 g i v e s a 12-b i t p w m wi t h a maxim u m o u t p u t ra t e o f 3 072 h z (12.583 mh z/4096). pwm0h / l s e ts t h e d u ty c y cle o f t h e p w m o u t p u t w a v e fo r m as sh ow n i n fi g u re 3 9 . p2.5 pwm counter pwm1h/l 0 pwm0h/l 04741-039 f i g u re 39. p w m in m o de 1 mo de 2 ( t win 8 - bit pwm) i n m o de 2, t h e d u ty c y cle a n d t h e r e s o l u t i on o f t h e p w m o u t p uts a r e p r o g ra mma b l e. t h e max i m u m r e s o l u t i o n o f t h e pwm o u t p u t is 8 b i ts. p w m 1 l se t s th e pe ri od f o r b o th p w m o u t p u t s . t y p i c a ll y , t h i s is s e t t o 255 (ffh) t o g i v e a n 8-b i t p w m, al t h oug h i t is p o s s ib l e t o r e d u ce this as n e ces s a r y . a va l u e o f 100 co u l d be lo ade d h e r e t o gi v e a pe r c en ta g e pw m, tha t i s , th e pw m i s a c cura t e t o 1% . the out p uts of t h e p w m a t p2. 5 and p2. 6 a r e sho w n i n f i gure 4 0 . a s can be s e en, th e ou t p u t o f p w m0 (p2.5) g o es lo w w h en t h e pw m c o un t e r e q u a ls pwm 0 l . th e o u t p u t o f pw m1 (p 2 . 6 ) g o e s hig h w h en t h e pwm co u n t e r e q uals p w m1h a nd g o es lo w a g a i n wh en th e pw m c o un t e r e q u a ls pwm 0 h . s e t t in g pwm 1 h to 0 e n su re s t h a t b o t h p w m out p u t s st ar t s i m u lt ane o u sly . p2.6 p2.5 pwm counter pwm1h 0 pwm1l pwm0h pwm0l 04741-040 f i g u re 40. p w m m o de 2
aduc845/aduc847/aduc848 rev. b | page 58 of 108 mo de 3 ( t win 1 6 -bit pwm) i n m o de 3, t h e pwm co u n t e r is f i xed t o co un t f r o m 0 t o 65536, g i vin g a f i xed 1 6 -b i t p w m. o p era t in g f r o m t h e 12.58 mh z co r e c l o c k r e s u l t s in a pwm o u t p u t ra t e o f 192 h z . the d u ty c y c l e o f th e pwm o u t p u t s a t p2.5 and p2.6 a r e in de p e n d en tl y p r o g ra mma b l e. a s sho w n in f i g u r e 41, while t h e pwm co u n t e r is les s tha n pwm0h / l, t h e o u t p u t o f p w m0 (p2.5) is hig h . o n ce t h e pwm co u n t e r e q uals p w m0h/l, pwm0 (p2.5 ) g o es lo w a nd r e ma in s lo w u n t i l the pwm co u n t e r r o l l s o v er . simi la rl y , w h i l e t h e pwm co u n ter is les s t h a n p w m1h/ l, t h e o u t p u t o f pwm 1 (p2.6) is hig h . on ce t h e p w m co un t e r eq ua ls pwm1h / l, p w m1 (p2.6) g o es lo w an d r e main s lo w u n til the pwm co u n t e r rol l s o v er . i n th is m o d e , b o th pw m o u t p u t s a r e syn c h r o n iz ed , th a t i s , o n ce th e pwm co un t e r r o ll s o v e r t o 0, bo th pwm 0 (p2 . 5 ) a n d pw m1 (p2.6) g o hig h . p2.6 p2.5 pwm counter pwm1h/l 0 65536 pwm0h/l 04741-041 f i g u re 41. p w m m o de 3 mode 4 (d u a l nrz 16-bit - ? d a c) m o de 4 p r o v ides a hig h sp eed p w m o u t p u t simila r t o tha t o f a - ? d a c. t y p i ca l l y , t h is m o de is us e d wi t h t h e pwm clo c k eq ual t o 12.58 mh z. i n t h i s mo de, p 1 .0 a nd p1.1 a r e u p da te d e v er y pwm clo c k (80 n s in t h e cas e o f 12.58 mh z) . o v er a n y 65536 c y c l es (16-b i t pwm), p w m0 (p1.0) is hig h f o r pwm0h/l c y c l es a nd lo w f o r (65536 C pwm 0 h/l) c y c l es. s i mila rl y , pwm1 (p1.1) is hig h f o r pwm1h / l c y c l es a nd lo w f o r (65536 C pwm1 h/l) c y c l es. i f pwm1h is s e t t o 4010h (s lig h tl y a b o v e on e-q u a r t e r o f fs), ty p i c a l l y p1.1 is lo w fo r t h r e e clo c ks an d hig h fo r o n e clo c k (eac h c l o c k is a p p r o x ima t e l y 8 0 n s ). o v er ev er y 65536 c l o c ks, th e pw m co m p r o m i se s f o r th e fa ct th a t t h e o u t p u t sh o u ld be s l ig h t l y abo v e on e-q u a r t e r o f f u l l s c ale , b y ha vin g a hig h c y c l e f o l l o w e d b y o n ly tw o lo w c y c l es. 12.583mhz 16-bit 80 s 0 16-bit 16-bit 16-bit 16-bit 16-bit carry out at p2.5 carry out at p2.6 pwm0h/l = c000h pwm1h/l = 4000h 0 1 00 latch 0 11 1 1 1 0 04741- 042 80 s f i g u re 42. p w m m o de 4 f o r fas t er d a c o u t p uts (a t lo we r r e s o l u t i o n ), w r i t e 0s t o t h e l s bs th a t a r e n o t r e q u i r ed wi th a 1 i n th e l s b p o si ti o n . i f , f o r exa m p l e , o n l y 1 2 -b i t p e r f o r ma nce is r e q u ir ed , wr i t e 0001 t o t h e 4 ls bs. this me a n s tha t a 12-b i t acc u ra t e - d a c o u t p u t can o c c u r a t 3 kh z. s i mi la rl y , wr i t ing 00000001 t o th e 8 ls b s g i v e s a n 8-b i t acc u ra te - d a c o u t p u t a t 49 kh z.
aduc845/aduc847/aduc848 rev. b | page 59 of 108 mo de 5 ( d u a l 8 - bit pwm) i n m o de 5, t h e d u ty c y cl e and t h e r e s o l u t i on of t h e p w m ou tpu t s a r e indivi d u a l ly p r o g ra mma b l e. the max i m u m r e s o l u t i o n o f t h e pwm o u t p u t is 8 b i ts. p2.6 p2.5 pwm counters pwm1h 0 pwm1l pwm0h pwm0l 04741-043 f i g u re 43. p w m m o de 5 mo de 6 ( d u a l rz 16-bit -? da c ) m o de 6 p r o v ides a hig h sp eed p w m o u t p u t simila r t o tha t o f a - d a c. m o de 6 o p era t es v e r y simila rl y t o m o de 4; h o wev e r , t h e ke y dif f er en ce is t h a t m o de 6 p r o v ides r e t u r n t o zer o (rz) - d a c ou t p ut. m o de 4 p r o v i d es n o n-r e t u r n - t o - zer o - d a c o u t p u t s. rz mo de en s u r e s tha t an y dif f er e n ce in the r i s e a nd fal l tim e s do es n o t a f f e c t t h e - d a c inl . h o w e v e r , rz m o de hal v es t h e d y na mic ra n g e o f t h e - d a c o u t p uts f r o m 0 v? t o a v dd d o w n to 0 v to a v dd /2 . f o r b e st re su l t s , t h is m o de sh o u l d b e us e d w i t h a p w m clo c k divi der o f 4. i f pwm1h is s e t t o 4010h (s lig h tl y a b o v e on e-q u a r t e r o f fs), typ i c a l l y p2.6 is lo w f o r thr e e f u ll c l o c ks (3 80 n s ), hig h f o r o n e-half a c l o c k (40 n s ), a nd t h e n lo w a g a i n f o r o n e-half a c l o c k (40 n s ) bef o r e r e p e a t in g i t s e lf . o v er ev er y 655 36 c l o c ks, t h e pw m co m p r o m i se s f o r th e fact th a t th e o u t p u t sh o u ld be s l ig h t l y ab o v e on e - q u a r t e r o f f u l l s c ale b y le a v ing t h e ou t p u t hig h f o r tw o hal f c l o c ks in f o ur ev er y s o o f t e n. f o r fas t er d a c o u t p uts (a t lo we r r e s o l u t i o n ), w r i t e 0s t o t h e l s bs th a t a r e n o t r e q u i r ed wi th a 1 i n th e l s b p o si ti o n . i f , f o r exa m p l e , o n l y 1 2 -b i t p e r f o r ma nce is r e q u ir ed , wr i t e 0001 t o t h e 4 ls bs. this me a n s tha t a 12-b i t acc u ra t e - d a c o u t p u t can o c c u r a t 3 kh z. s i mi la rl y , wr i t ing 00000001 t o th e 8 ls b s g i v e s a n 8-b i t acc u ra te - d a c o u t p u t a t 49 kh z. t h e output re s o lut i on i s s e t b y t h e p w m 1 l a n d p w m 1 h sf r s f o r th e p2 .5 a n d p 2 .6 o u t p u t s , r e s p e c ti v e l y . pw m0 l a n d pwm 0 h s e t t h e d u ty c y cl es o f t h e p w m o u t p uts a t p2 .5 a nd p2.6, re sp e c t i v e ly . b o t h p w m s ha v e t h e s a me cl o c k s o u r c e and cl o c k divid e r . 3.146mhz 16-bit 318 s 0 16-bit 16-bit 16-bit 16-bit 16-bit carry out at p2.5 carry out at p2.6 pwm0h/l = c000h pwm1h/l = 4000h 0 1 0 00 0 latch 0 11 1 1 1 0 318 s 0, 3/4, 1/2, 1/4, 0 04741-044 f i g u re 44. p w m m o de 6 mo de 7 i n m o de 7, t h e pwm is dis a b l e d , a l lo wi n g p2.5 a nd p2.6 to b e us ed as n o r m al .
aduc845/aduc847/aduc848 rev. b | page 60 of 108 on-chip pll (pllcon) the aduc845/aduc847/ad uc848 are intended for use with a 32.768 khz watch crystal. a pll locks onto a multiple (384) of this to provide a stable 12.582912 mhz clock for the system. the core can operate at this frequency or at binary submultiples of it to allow power saving when maximum core performance is not required. the default core clock is the pll clock divided by 8 or 1.572864 mhz. the adc clocks are also derived from the pll clock, with the modulator rate being the same as the crystal oscillator frequency. the control register for the pll is called pllcon and is described as follows. the 5 v parts can be set to a maximum core frequency of 12.58 mhz (cd2...0 = 000) while at 3 v, the maximum core clock rate is 6.29 mhz (cd2...0 = 001). the cd bits should not be set to 000b on the 3 v parts. the 3 v parts are limited to a core clock speed of 6.29 mhz (cd = 1). pllcon pll control register sfr address: d7h power-on default: 53h bit addressable: no table 39. pllcon pll control register bit no. name description 7 osc_pd oscillator power-down bit. if low, the 32 khz crystal oscillator continues running in power-down mode. if high, the 32.768 khz oscillator is powered down. when this bit is low, the seconds counter continues to count in power-down mode and can interrupt the cpu to exit power-down. the oscillator is always enabled in normal mode. 6 lock pll lock bit. this is a read-only bit. set automatically at power-on to indicate that the pll l oop is correctly tracking the crystal clock. after power- down, this bit can be polled to wait for the pll to lock. cleared automatically at power-on to indicate that the pll is not correctly tracking the crystal clock. this might be due to the absence of a crystal clock or an ex ternal crystal at power-on. in this mode, the pll output can be 12.58 mhz 20%. after the part wakes up from power -down, user code can poll this bit to wait for the pll to lock. if lock = 0, the pll is not locked. 5 CCC not implemented. write dont care. 4 ltea ea status. read-only bit. reading this bit returns the state of the external ea pin latched at reset or power-on. 3 fint fast interrupt response bit. set by the user to enable the respon se to any interrupt to be executed at the fastest core clock frequency. cleared by the user to disable the fast interrupt response feature. this function must not be used on 3 v parts. cpu (core clock) divider bits. this number determines the frequency at which the core operates. cd2 cd1 cd0 core clock frequency (mhz) 0 0 0 12.582912. not a valid selection on 3 v parts. 0 0 1 6.291456 (maximum core clock rate allowed on the 3 v parts) 0 1 0 3.145728 0 1 1 1.572864 (default core frequency) 1 0 0 0.786432 1 0 1 0.393216 1 1 0 0.196608 2, 1, 0 cd2, cd1, cd0 1 1 1 0.098304 on 3 v parts (aduc84xbcpxx-3 or aduc84xbsxx-3), the cd settings can be only cd = 1; cd = 0 is not a valid selection. if cd = 0 is selected on a 3 v part by writ ing to pllcon, the instruction is ignored, and the previous cd value is retained. the fast interrupt bit (fint) must not be used on 3 v part s since it automatically sets the cd bits to 0, which is not a valid setting.
aduc845/aduc847/aduc848 rev. b | page 61 of 108 i 2 c serial interface the aduc845/aduc847/ aduc848 support a fully licensed i 2 c serial interface. the i 2 c interface is implemented as a full hardware slave and software master. sdata (pin 27 on the mqfp package and pin 29 on the lfcsp package) is the data i/o pin. sclk (pin 26 on the mqfp package and pin 28 on the lfcsp package) is the serial interface clock for the spi interface. the i 2 c interface on the parts is fully independent of all other pin/function multiplexing. the i 2 c interface incorporated on the aduc845/aduc847/aduc848 also includes a second address register (i2cadd1) at sfr address f2h with a default power-on value of 7fh. the i 2 c interface is always available to the user and is not multiplexed with any other i/o functionality on the chip. this means that the i 2 c and spi interfaces can be used at the same time. note that when using the i 2 c and spi interfaces simultaneously, they both use the same interrupt routine (vector address 3bh). when an interrupt occurs from one of these, it is necessary to interrogate each interface to see which one has triggered the isr request. the four sfrs that are used to control the i 2 c interface are described next. i2cconi 2 c control register sfr address: e8h power-on default: 00h bit addressable: yes table 40. i2ccon sfr bit designations bit no. name description 7 mdo i 2 c software master data output bit (master mode only). this data bit is used to implement a master i 2 c transmitter interface in software. da ta written to this bit is output on the sdata pin if the data output enable bit (mde) is set. 6 mde i 2 c software output enable bit (master mode only). set by the user to enable the sdata pin as an output (tx). cleared by the user to enable the sdata pin as an input (rx). 5 mco i 2 c software master clock output bit (master mode only). this bit is used to impleme nt the sclk for a master i 2 c transmitter in software. data wr itten to this bit is output on the sclk pin. 4 mdi i 2 c software master data input bit (master mode only). this data bit is used to implement a master i 2 c receiver interface in software. data on the sdata pin is latched into this bit on an sclk transition if th e data output enable (mde) bit is 0. 3 i2cm i 2 c master/slave mode bit. set by the user to enable i 2 c software master mode. cleared by the user to enable i 2 c hardware slave mode. 2 i2crs i 2 c reset bit (slave mode only). set by the user to reset the i 2 c interface. cleared by the user code for normal i 2 c operation. 1 i2ctx i 2 c direction transfer bit (slave mode only). set by the microconverter if the i 2 c interface is transmitting. cleared by the microconverter if the i 2 c interface is receiving. 0 i2ci i 2 c interrupt bit (slave mode only). set by the microconverter after a byte has been transmitted or received. cleared by the microconverter when the user code reads the i2cdat sfr. i2ci should not be cleared by user code.
aduc845/aduc847/aduc848 rev. b | page 62 of 108 i2cad d i 2 c a d d r ess r e gis t e r 1 f u nc t i o n : h o l d s one of t h e i 2 c p e r i ph eral addr es s e s fo r t h e p a r t . i t ma y b e o v er wr i t t e n b y us er co de . a p plica t io n n o t e u c 001 a t h t t p ://w w w .a nal o g.co m/micr o c o n v e r t er des c r i b e s t h e fo r m a t of t h e i 2 c st andar d 7-b i t ad dr ess. s f r a ddr ess: 9bh p o w e r - o n def a u l t: 55h bi t a d dress a bl e: n o i2cad d 1i 2 c a d d r ess r e gi s t e r 2 f u n c tion: sa me as t h e i2c a d d . s f r a ddr ess: f 2 h po w e r - o n d e f a u l t : 7 f h bi t a d dress a bl e: n o i2cd a t i 2 c da ta r e g i st e r f u n c tion: the i2c d a t s f r is wr i t ten t o b y us er co de t o tra n smi t da t a , o r r e ad b y us er co de t o r e ad da t a j u s t r e cei v ed b y th e i 2 c in t e r f ac e . a c ces s in g i2 cd a t a u t o ma tical l y c l ea rs a n y p e ndin g i 2 c in ter r u p t a n d t h e i 2 ci b i t i n t h e i2c c o n s f r . u s er co de sh o u ld acces s i2 cd a t o n l y o n c e p e r in t e r r u p t c y c l e . s f r a ddr ess: 9ah p o w e r - o n def a u l t: 00h bi t a d dress a bl e: n o the ma i n fe a t ures o f t h e micr o c o n v e r t er i 2 c i n t e r f ac e a r e ? onl y tw o b u s l i n e s a r e r e q u ir e d : a s e r i al da ta l i n e (s d a t a ) a nd a s e r i a l clo c k li n e (sclo c k). ? an i 2 c mast er c a n co mm uni c a t e w i t h m u l t i p le s l a v e de vices. b e c a us e e a ch s l a v e de v i ce has a u n iq ue 7-b i t addr ess, s i n g le master / s l a ve r e l a t i o n shi p s ca n e x ist a t a l l tim e s ev en in a m u l t i s l a v e en v i r o n m en t . ? th e abi l it y to re sp ond to t w o s e p a r a te a d dre s s e s w h e n o p e r a t in g in sla v e m o d e . ? on-chi p f i l t er ing r e je c t s <50 ns s p i k es o n t h e sd a t a and t h e s c l o c k li n e s t o p r es er v e da t a in t e g r i t y . dv dd i 2 c ma s t er i 2 c slave 1 i 2 c slave 2 04741-045 f i g u re 45. t y pic a l i 2 c s y st em s o f t w a re master mo de the adu c 845/aduc847/ adu c 848 ca n be us e d as a n i 2 c mast er d e v i ce b y co nf igur in g t h e i 2 c p e r i ph eral in mast er m o de a nd wr i t i n g s o f t wa r e t o o u t p u t t h e d a t a b i t- b y - b i t . this is r e f e r r ed t o as a s o f t wa r e mas t er . m a s t er m o de is ena b led b y s e t t in g t h e i2c m b i t in t h e i2c c o n r e g i s t er . t o t r a n s m i t d a ta o n th e s d a t a l i n e , m d e m u s t b e s e t t o e n a b le t h e ou t p u t dr iv e r o n t h e s d a t a p i n. i f md e is s e t, t h e s d a t a p i n is p u l l e d hig h o r lo w de p e ndin g on w h et h e r t h e md o b i t i s s e t or cl e a re d. m c o c o n t ro l s t h e s c lo c k p i n a n d i s a l w a y s co nf igur ed as an o u t p u t in mast er m o de . i n mas t er mo de, t h e scl o ck p i n is p u l l ed hig h o r lo w dep e n d in g on t h e w h et h e r mc o is s e t o r c l e a r e d. t o r e cei v e da t a , mde m u st b e cle a r e d to dis a b l e t h e o u tp u t dr i v er o n sd a t a. s o f t wa r e m u s t p r o v ide t h e clo c ks b y t o g g l ing t h e mc o b i t and r e adin g t h e sd a t a pin v i a t h e md i b i t. i f md e is c l ea r e d , md i ca n be us ed t o r e ad the s d a t a p i n. th e val u e o f t h e s d a t a p i n is la t c hed in t o md i o n a r i sin g edg e o f scl o ck. md i is s e t if t h e s d a t a p i n is hig h on t h e las t r i sin g e d ge o f sclo c k . mdi is cle a r e d if t h e sd a t a p i n is lo w o n t h e las t r i sin g e d g e o f scl o ck. s o f t w a re m u st c o n t ro l m d o , m c o , an d m d e appropr i a t ely to g e n e ra t e t h e s t ar t co n d i t io n, s l a v e addr ess, ack n o w le dg e b i ts, d a t a b y tes, and sto p co nd i t io n s . th e s e f u n c t i o n s a r e des c r i b e d in a p p l ica t io n n o t e u c 001.
aduc845/aduc847/aduc848 rev. b | page 63 of 108 hardware slave mode after reset, the aduc845/aduc847/aduc848 default to hardware slave mode. the i 2 c interface is enabled by clearing the spe bit in spicon. slave mode is enabled by clearing the i2cm bit in i2ccon. the parts have a full hardware slave. in slave mode, the i 2 c address is stored in the i2cadd register. data received or to be transmitted is stored in the i2cdat register. once enabled in i 2 c slave mode, the slave controller waits for a start condition. if the parts detect a valid start condition, followed by a valid address, followed by the r/w bit, then the i2ci interrupt bit is automatically set by hardware. the i 2 c peripheral generates a core interrupt only if the user has pre- configured the i 2 c interrupt enable bit in the ieip2 sfr as well as the global interrupt bit, ea, in the ie sfr. therefore, mov ieip2, #01h ;enable i 2 c interrupt setb ea an autoclear of the i2ci bit is implemented on the parts so that this bit is cleared automatically upon read or write access to the i2cdat sfr. mov i2cdat, a ;i2ci auto-cleared mov a, i2cdat ;i2ci auto-cleared if for any reason the user tries to clear the interrupt more than once, that is, access the data sfr more than once per interrupt, the i 2 c controller stops. the interface then must be reset by using the i2crs bit. the user can choose to poll the i2ci bit or to enable the interrupt. in the case of the interrupt, the pc counter vectors to 003bh at the end of each complete byte. for the first byte, when the user gets to the i2ci isr, the 7-bit address and the r/w bit appear in the i2cdat sfr. the i2ctx bit contains the r/w bit sent from the master. if i2ctx is set, the master is ready to receive a byte; therefore the slave transmits data by writing to the i2cdat register. if i2ctx is cleared, the master is ready to transmit a byte; therefore the slave receives a serial byte. software can interrogate the state of i2ctx to determine whether it should write to or read from i2cdat. once the part has received a valid address, hardware holds sclock low until the i2ci bit is cleared by software. this allows the master to wait for the slave to be ready before transmitting the clocks for the next byte. the i2ci interrupt bit is set every time a complete data byte is received or transmitted, provided that it is followed by a valid ack. if the byte is followed by a nack, an interrupt is not generated. the part continues to issue interrupts for each complete data byte transferred until a stop condition is received or the interface is reset. when a stop condition is received, the interface resets to a state in which it is waiting to be addressed (idle). similarly, if the interface receives a nack at the end of a sequence, it also returns to the default idle state. the i2crs bit can be used to reset the i 2 c interface. this bit can be used to force the interface back to the default idle state.
aduc845/aduc847/aduc848 rev. b | page 64 of 108 spi serial interface the aduc845/aduc847/ aduc848 integrate a complete hardware serial peripheral interface (spi) interface on-chip. spi is an industry-standard synchronous serial interface that allows 8 bits of data to be synchronously transmitted and received simultaneously, that is, full duplex. note that the spi pins are multiplexed with the port 2 pins, p2.0, p2.1, p2.2, and p2.3. these pins have spi functionality only if spe is set. otherwise, with spe cleared, standard port 2 functionality is maintained. spi can be configured for master or slave operation and typically consists of pins sclock, miso, mosi, and ss . sclock (serial clock i/o pin) pin 28 (mqfp package), pin 30 (lfcsp package) the master clock (sclock) is used to synchronize the data transmitted and received through the mosi and miso data lines. a single data bit is transmitted and received in each sclock period. therefore, a byte is transmitted/received after eight sclock periods. the sclock pin is configured as an output in master mode and as an input in slave mode. in master mode, the bit rate, polarity, and phase of the clock are controlled by the cpol, cpha, spr0, and spr1 bits in the spicon sfr (see table 41). in slave mode, the spicon register must be config- ured with the same phase and polarity (cpha and cpol) as the master. the data is transmitted on one edge of the sclock signal and sampled on the other. miso (master in, slave out pin) pin 30 (mqfp package), pin 32 (lfcsp package) the miso pin is configured as an input line in master mode and an output line in slave mode. the miso line on the master (data in) should be connected to the miso line in the slave device (data out). the data is transferred as byte-wide (8-bit) serial data, msb first. mosi (master out, slave in pin) pin 29 (mqfp package), pin31 (lfcsp package) the mosi pin is configured as an output line in master mode and an input line in slave mode. the mosi line on the master (data out) should be connected to the mosi line in the slave device (data in). the data is transferred as byte-wide (8-bit) serial data, msb first. ss (slave select input pin) pin 31 (mqfp package), pin 33 (lfcsp package) the ss pin is used only when the aduc845/aduc847/ aduc848 are configured in spi slave mode. this line is active low. data is received or transmitted in slave mode only when the ss pin is low, allowing the parts to be used in single-master, multislave spi configurations. if cpha = 1, the ss input can be pulled low permanently. if cpha = 0, the ss input must be driven low before the first bit in a byte-wide transmission or reception and must return high again after the last bit in that byte-wide transmission or reception. in spi slave mode, the logic level on the external ss pin (pin 31/pin 33) can be read via the spr0 bit in the spicon sfr. the sfr register in table 41 is used to control the spi interface.
aduc845/aduc847/aduc848 rev. b | page 65 of 108 spiconspi control register sfr address: f8h power-on default: 05h bit addressable: yes table 41. spicon sfr bit designations bit no. name description 7 ispi spi interrupt bit. set by the microconverter at the end of each spi transfer. cleared directly by user code or indirectly by reading the spidat sfr. 6 wcol write collision error bit. set by the microconverter if spidat is written to while an spi transfer is in progress. cleared by user code. 5 spe spi interface enable bit. set by user code to enable spi functionality. cleared by user code to enable standard port 2 functionality. 4 spim spi master/slave mode select bit. set by user code to enable master mode operation (sclock is an output). cleared by user code to enable slave mode operation (sclock is an input). 3 cpol 1 clock polarity bit. set by user code to enable sclock idle high. cleared by user code to enable sclock idle low. 2 cpha 1 clock phase select bit. set by user code if the leading sc lock edge is to transmit data. cleared by user code if the trailing sclock edge is to transmit data. spi bit-rate bits. spr1 spr0 selected bit rate 0 0 f core /2 0 1 f core /4 1 0 f core /8 1, 0 spr1, spr0 1 1 f core /16 1 the cpol and cpha bits should both contain the same values for master and slave devices. note that both spi and i 2 c use the same isr (vector address 3bh); therefore, when using spi and i 2 c simultaneously, it is necessary to check the interfaces following an interrupt to determine which one caused the interrupt. spidat: spi data register sfr address: 7fh power-on default: 00h bit addressable: no
aduc845/aduc847/aduc848 rev. b | page 66 of 108 using the s p i interf a c e d e p e nding o n t h e co nf igur a t ion o f t h e b i ts i n t h e spi c on s f r sh o w n in t a b l e 41, t h e sp i in t e r f ace t r a n s m i t s o r r e cei v es da ta in a n u m b e r o f p o s s i b le m o des. f i gur e 46 sh o w s al l p o s s i b le aduc845/aduc847 /aduc848 s p i c o nf igura t io n s a nd t h e t i mi n g r e la t i o n shi p s and sy n c hr o n i z a t i o n a m on g t h e sig n als in v o l v e d . als o sh o w n in this f i gur e is the s p i in t e r r u p t b i t (ispi) a nd ho w i t is t r ig ger e d a t t h e e n d o f e a ch b y te- w i d e co mm un ic a t io n . sclock ( c pol = 1) sclock ( c pol = 0) ( c pha = 1) ( c pha = 0) sample input ispi flag data output ispi flag sample input data output ? msb bit 6 bit 5 bit 4 b it 3 b it 2 b it 1 l sb msb b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 lsb ss 04741-046 f i g u re 46. spi tim i ng , a l l m o d e s spi inter f a c emast er mo de i n mas t er m o de, th e s c l o c k p i n is alwa ys an ou t p u t an d g e n e ra t e s a b u rst o f eig h t clo c ks w h e n e v er us er c o de wr i t es t o t h e s p i d a t r e g i s t er . th e s c l o ck b i t ra t e is de t e r m i n e d b y s p r0 an d s p r1 in s p i c o n . als o n o t e t h a t t h e ss pi n i s not us e d i n mas t er m o de . i f t h e p a r t s n e e d t o ass e r t t h e ss pi n o n an ext e r n al s l a v e de v i ce , a p o r t dig i t a l o u t p ut p i n sh o u ld b e us e d . i n ma st er m o d e , a b y te t r a n smi s sio n o r r e cep t i o n is in i t ia te d b y a b y t e w r i t e to spi d a t . th e h a rdw a re a u toma t i c a l l y ge ne r a te s eig h t clo c k p e r i o d s v i a t h e sclo ck p i n, and t h e da t a is tra n sm i t t e d via m o s i . w i th ea ch sc l o ck pe riod , a da t a b i t i s al so sa m p l e d via mi s o . a f t e r ei gh t c l o c k s , t h e tra n s m i t t e d b y t e is co m p lete l y tra n smi t t e d (via m o s i ), a n d t h e in p u t b y t e (if r e q u ir e d ) is wai t in g i n t h e in put shif t reg i st er ( a f t er b e i n g r e ce i v ed vi a miso ). th e is p i f l a g i s set a u t o m a ti call y , a n d a n in t e r r u p t o c c u rs if ena b le d . t h e va l u e in t h e in p u t sh if t r e g i ste r i s l a tc he d i n to spi d a t . spi inter f a c esla v e mode i n sl a v e m o de , t h e scl o ck is a n i n p u t . th e ss pi n m u s t a l s o be d r i v e n l o w ex t e rn all y d u ri n g th e b y t e c o m m u n i c a t i o n . t r a n s - missio n is a l s o i n i t ia t e d b y a wr i t e t o s p i d a t . i n sla v e mo de, a da ta b i t i s tra n sm i t t e d via miso , a n d a da ta b i t i s r e ce i v ed vi a mos i t h r o ug h e a ch i n p u t sclo ck p e r i o d . af t e r eig h t clo c ks , t h e t r a n s m it te d b y te i s c o m p l e t e ly t r ans m i tte d, a nd t h e i n put b y t e is wa i t in g i n t h e i n p u t sh if t r e g i st er . t h e ispi f l a g is s e t a u t o m a t i c a l l y , and a n in ter r u p t o c c u rs, if ena b le d . t h e va l u e in t h e sh if t re g i ste r is l a tc he d i n to s p i d a t on ly w h e n t h e t r ans - missio n / r e cep t i o n o f a b y te has b e e n co m p le te d. the e n d o f t r a n smissio n o c c u rs a f t e r t h e ei g h t h clo c k has b e e n r e cei v e d if cp h a = 1, o r w h e n ss r e t u r n s hig h if cph a = 0.
aduc845/aduc847/aduc848 rev. b | page 67 of 108 dual data pointers the parts incorporate two data pointers. the second data pointer is a shadow data pointer and is selected via the data pointer control sfr (dpcon). dpcon features automatic hardware post-increment and post-decrement as well as an automatic data pointer toggle. dpcondata pointer control sfr sfr address: a7h power-on default: 00h bit addressable: no table 42. dpcon sfr bit designations bit no. name description 7 ---- not implemented. write dont care. 6 dpt data pointer automatic toggle enable. cleared by the user to disable autoswapping of the dptr. set in user software to enable automatic toggling of the dptr after each movx or movc instruction. shadow data pointer mode. these bits enable extra mo des of the shadow data pointer operation, allowing more compact and more effici ent code size and execution. dp1m1 dp1m0 behavior of the shadow data pointer 0 0 8052 behavior. 0 1 dptr is post-incremented after a movx or a movc instruction. 1 0 dptr is post-decremented after a movx or movc instruction. 5, 4 dp1m1, dp1m0 1 1 dptr lsb is toggled after a movx or movc inst ruction. (this instruction can be useful for moving 8-bit blocks to/from 16-bit devices.) main data pointer mode. these bits enable extra mode s of the main data pointer operation, allowing more compact and more efficient code size and execution. dp0m1 dp0m0 behavior of the main data pointer 0 0 8052 behavior. 0 1 dptr is post-incremented after a movx or a movc instruction. 1 0 dptr is post-decremented after a movx or movc instruction. 3, 2 dp0m1, dp0m0 1 1 dptr lsb is toggled after a movx or movc in struction. (this instruction is useful for moving 8-bit blocks to/from 16-bit devices.) 1 ---- not implemented. write dont care. 0 dpsel data pointer select. cleared by the user to select the main data pointer. th is means that the contents of this 24-bit register are placed into the dpl, dph, and dpp sfrs. set by the user to select the shadow data pointer. this means that the contents of a separate 24-bit register appear in the dpl, dph, and dpp sfrs. note the following: ? the dual data pointer section is the only place in which main and shadow data pointers are distinguished. whenever the dptr is mentioned elsewhere in this data sheet, active dptr is implied. ? only the movc/movx @dptr instructions automatically post-increment and post-decrement the dptr. other movc/movx instructions, such as movc pc or movc @ri, do not cause the dptr to automatically post-increment and post-decrement. to illustrate the operation of dpcon, the following code copies 256 bytes of code memory at address d000h into xram, starting from address 0000h. mov dptr,#0 ;main dptr = 0 mov dpcon,#55h ;select shadow dptr ;dptr1 increment mode ;dptr0 increment mode ;dptr auto toggling on mov dptr,#0d000h ;dptr = d000h moveloop: clr a movc a,@a+dptr ;get data ;post inc dptr ;swap to main dptr(data) movx @dptr,a ;put acc in xram ;increment main dptr ;swap shadow dptr(code) mov a, dpl jnz moveloop
aduc845/aduc847/aduc848 rev. b | page 68 of 108 power supply monitor the power supply monitor, once enabled, monitors the dv dd and av dd supplies on the parts. it indicates when any of the supply pins drop below one of four user-selectable voltage trip points from 2.63 v to 4.63 v. for correct operation of the power supply monitor function, av dd must be equal to or greater than 2.63 v. monitor function is controlled via the psmcon sfr. if enabled via the ieip2 sfr, the monitor interrupts the core by using the psmi bit in the psmcon sfr. this bit is not cleared until the failing power supply returns above the trip point for at least 250 ms. the monitor function allows the user to save working registers to avoid possible data loss due to the low supply condition, and also ensures that normal code execution does not resume until a safe supply level is well established. the supply monitor is also protected against spurious glitches triggering the interrupt circuit. the 5 v part has an internal por trip level of 4.63 v, which means that there are no usable dv dd psm trip levels on the 5 v part. the 3 v part has a por trip level of 2.63 v following a reset and initialization sequence, allowing all relevant psm trip points to be used. psmconpower supply monitor control register sfr address: dfh power-on default: deh bit addressable: no table 43. psmcon sfr bit designations bit no. name description 7 cmpd dv dd comparator bit. this read-only bit directly reflects the state of the dv dd comparator. read 1 indicates that the dv dd supply is above its selected trip point. read 0 indicates that the dv dd supply is below its selected trip point. 6 cmpa av dd comparator bit. this read-only bit directly reflects the state of the av dd comparator. read 1 indicates that the av dd supply is above its selected trip point. read 0 indicates that the av dd supply is below its selected trip point. 5 psmi power supply monitor interrupt bit. set high by the microconverter if either cmpa or cmpd is low, indicating low analog or digital supply. the psmi bit can be used to interrupt the processor. once cm pd and/or cmpa returns (and remains) high, a 250 ms counter is started. when this counter times out, the psmi interrupt is cleared. psmi can also be written by the user. however, if either comparator output is low, it is not possible for the user to clear psmi. dv dd trip point selection bits. a 5 v part has no valid psm trip points. if the dv dd supply falls below the 4.63 v point, the part resets (por). for a 3 v part, all relevant psm trip points are valid. the 3 v por trip point is 2.63 v (fixed). these bits select the dv dd trip point voltage as follows: tpd1 tpd0 selected dv dd trip point (v) 0 0 4.63 0 1 3.08 1 0 2.93 4, 3 tpd1, tpd0 1 1 2.63 av dd trip point selection bits. these bits select the av dd trip point voltage as follows: tpa1 tpa0 selected av dd trip point (v) 0 0 4.63 0 1 3.08 1 0 2.93 2, 1 tpa1, tpa0 1 1 2.63 0 psmen power supply monitor enable bit. set to 1 by the user to enable the power supply monitor circuit. cleared to 0 by the user to disable the power supply monitor circuit.
aduc845/aduc847/aduc848 rev. b | page 69 of 108 watchdog timer the watchdog timer generates a device reset or interrupt within a reasonable amount of time if the aduc845/aduc847/ aduc848 enters an erroneous state, possibly due to a program- ming error or electrical noise. the watchdog function can be disabled by clearing the wde (watchdog enable) bit in the watchdog control (wdcon) sfr. when enabled, the watchdog circuit generates a system reset or interrupt (wds) if the user program fails to set the wde bit within a predetermined amount of time (see the pre30 bits in table 44). the watchdog timer is clocked from the 32 khz external crystal connected between the xtal1 and xtal2 pins. the wdcom sfr can be written only by user software if the double write sequence described in wdwr is initiated on every write access to the wdcon sfr. wdconwatchdog control register sfr address: c0h power-on default: 10h bit addressable: yes table 44. wdcon sfr bit designations bit no. name description watchdog timer prescale bits. the watchdog timeout period is given by the equation t wd = (2 pre (2 9 / f xtal )) (0 pre 7; f xtal = 32.768 khz) pre3 pre2 pre1 pre0 timeout period (ms) action 0 0 0 0 15.6 reset or interrupt 0 0 0 1 31.2 reset or interrupt 0 0 1 0 62.5 reset or interrupt 0 0 1 1 125 reset or interrupt 0 1 0 0 250 reset or interrupt 0 1 0 1 500 reset or interrupt 0 1 1 0 1000 reset or interrupt 0 1 1 1 2000 reset or interrupt 1 0 0 0 0.0 immediate reset 7, 6, 5, 4 pre3, pre2, pre1, pre0 pre3Cpre0 > 1000b reserved. not a valid selection. 3 wdir watchdog interrupt response enable bit. if this bit is set by the user, the watchdog genera tes an interrupt response instead of a system reset when the watchdog timeout period expires. this in terrupt is not disabled by the clr ea instruction, and it is also a fixed, high priori ty interrupt. if the watchdog time r is not being used to monitor the system, it can be used alternatively as a timer. th e prescaler is used to set the timeout period in which an interrupt is generated. 2 wds watchdog status bit. set by the watchdog controller to indicate that a watchdog timeout has occurred. cleared by writing a 0 or by an external hardware reset. it is not cleared by a watchdog reset. 1 wde watchdog enable bit. set by the user to enable the watchdog and clear its counters. if this bit is not set by the user within the watchdog timeout period, the watchdog timer generates a reset or interrupt, depending on wdir. cleared under the following conditions: user writes 0; watchdog reset (wdir = 0); hardware reset; psm interrupt. 0 wdwr watchdog write enable bit. writing data to the wdcon sfr involves a double instruction sequence. global interrupts must first be disabled. the wdwr bit is set with the very next instruction, a write to the wdcon sfr. for example: clr ea ;disable interrupts while configuring to wdt setb wdwr ;allow write to wdcon mov wdcon, #72h ;enable wdt for 2.0s timeout setb ea ;enable interrupts again (if required)
aduc845/aduc847/aduc848 rev. b | page 70 of 108 time in terv al c o un t e r ( t ic ) a t i c i s prov i d e d on - c h i p f o r c o u n t i ng l o nge r i n te r v a l s t h a n th e s t anda r d 80 51-co m p a t i b l e t i mers can co un t. the ti c is ca p a b l e o f t i m e o u t in t e r v als ra n g in g f r o m 1/1 28 s e co nd t o 25 5 h o urs. als o , this co un t e r is c l o c k e d b y the ext e r n al 32.768 kh z cr ys tal ra th e r tha n b y th e co r e c l oc k , a n d i t ca n r e m a i n a c t i v e in p o w e r - do wn mo de an d t i m e lon g p o w e r - do w n in ter v a l s. this has ob vio u s a p plica t io n s fo r r e m o te ba t t er y-p o w e r e d s e ns o r s w h er e r e gu la r w i de l y s p ace d r e adin gs a r e r e q u ire d . n o t e t h a t in s t r u c t io n s t o t h e ti c s f rs a r e als o c l o c k e d a t 32.768 kh z, s o s u f f i c i en t t i me m u s t b e al lo w e d i n u s er c o de fo r t h e s e ins t r u c t ion s to e x e c ute. s i x s f r s a r e a s soci a t ed w i th th e t i m e i n t e r v al co u n t e r , t i me con b e i n g it s c o n t ro l re g i ste r . d e p e nd i n g on t h e co nf igura t io n of t h e it 0 a n d it 1 b i t s i n t i me co n , th e se le ct ed tim e co un t e r r e g i s t e r o v e r f l o w cl o c k s t h e i n te r v a l c o u n te r . whe n th i s co un t e r i s eq ual t o th e tim e i n t e r v al v a l u e loa d ed in t h e int v al s f r , t h e tii b i t (ti m ec o n .2) is s e t a nd g e n e ra t e s an in t e r r u p t, if enab le d . i f t h e p a r t is in p o w e r - do w n m o d e , a g ain wi th ti c in t e r r u p t ena b le d , t h e tii b i t wak e s u p th e de vic e and r e s u m e s co d e ex ecu t i o n b y v e c t o r i n g di r e ctl y t o th e t i c in t e r r u p t s e r v ic e v e c t o r addr es s a t 0053h. the ti c-re l a t e d s f rs a r e d e sc ri be d in t a b l e 4 5 . n o t e al so th a t t h e t i m e ba se d s f r s c a n b e w r i t t e n i n i t i a ll y w i th th e cu rr e n t t i m e ; th e t i c c a n th e n be co n t r o ll ed a n d a c ce s s ed b y use r so ft w a r e . i n e f f e ct , th i s faci li t a t e s t h e i m ple m en t a t i on o f a r e a l -t i m e clo c k. a b a sic b l o c k d i ag r a m of t h e t i c i s s h ow n i n f i g u re 4 7 . b e ca us e t h e tic is clo c k e d dire c t ly f r o m a 32 khz ext e r n a l cr ys tal o n th e p a r t s, i n s t r u cti o n s th a t a c ce s s t h e t i c r e gi st e r s a r e als o clo c k e d a t 32 kh z ( n o t a t t h e co r e f r e q uen c y). the us e r m u st e n su re t h a t su f f i c i e n t t i me is g i ve n for t h e s e inst r u c t ions to e x e c ute. 8-bit prescaler hundredths counter hthsec second counter sec minute counter min hour counter hour tien interval timeout time interval counter interrupt 8-bit interval counter intval sfr interval timebase selection mux tcen 32.768khz external crystal its0 its1 equal? 04741-047 f i g u re 47. tic s i mp lif i e d b l o c k d i ag r a m
aduc845/aduc847/aduc848 rev. b | page 71 of 108 timecontic control register sfr address: a1h power-on default: 00h bit addressable: no table 45. timecon sfr bit designations bit no. name description 7 ---- not implemented. write dont care. 6 tfh twenty-four hour select bit. set by the user to enable the hour counter to count from 0 to 23. cleared by the user to enable the ho ur counter to count from 0 to 255. 5, 4 its1, its0 interval timebase selection bits. its1 its0 interval timebase 0 0 1/128 second 0 1 seconds 1 0 minutes 1 1 hours 3 st1 single time interval bit. set by the user to generate a single interval t imeout. if set, a timeout clears the tien bit. cleared by the user to allow the interval counter to be automatically reloaded and start counting again at each interval timeout. 2 tii tic interrupt bit. set when the 8-bit interval counter matches the value in the intval sfr. cleared by user software. 1 tien time interval enable bit. set by the user to enable the 8-bit time interval counter. cleared by the user to disable the interval counter. 0 tcen time clock enable bit. set by the user to enable the time clock to the time interval counters. cleared by the user to disable the clock to the time interv al counters and reset the time interval sfrs to the last value written to them by the user. the time registers (hth sec, sec, min, and hour) can be written while tcen is low.
aduc845/aduc847/aduc848 rev. b | page 72 of 108 intvaluser timer interval select register function: user code writes the required time interval to this register. when the 8-bit interval counter is equal to the time interval value loaded in the intval sfr, the tii bit (timecon.2) is set and generates an interrupt, if enabled. sfr address: a6h power-on default: 00h bit addressable: no valid value: 0 to 255 decimal hthsechundredths of seconds time register function: this register is incremented in 1/128-second intervals once tcen in timecon is active. the hthsec sfr counts from 0 to 127 before rolling over to increment the sec time register. sfr address: a2h power-on default: 00h bit addressable: no valid value: 0 to 127 decimal secseconds time register function: this register is incremented in 1-second intervals once tcen in timecon is active. the sec sfr counts from 0 to 59 before rolling over to increment the min time register. sfr address: a3h power-on default: 00h bit addressable: no valid value: 0 to 59 decimal minminutes time register function this register is incremented in 1-minute intervals once tcen in timecon is active. the min sfr counts from 0 to 59 before rolling over to increment the hour time register. sfr address: a4h power-on default: 00h bit addressable: no valid value: 0 to 59 decimal hourhours time register function: this register is incremented in 1-hour intervals once tcen in timecon is active. the hour sfr counts from 0 to 23 before rolling over to 0. sfr address: a5h power-on default: 00h bit addressable: no valid value: 0 to 23 decimal to enable the tic as a real-time clock, the hour, min, sec, and hthsec registers can be loaded with the current time. once the tcen bit is high, the tic starts. to use the tic as a time interval counter, select the count intervalhundredths of seconds, s econds, minutes, and hours via the its0 and its1 bits in the timecon sfr. load the count required into the intval sfr. note that intval is only an 8-bit register, so user software must take into account any intervals longer than are possible with 8 bits. therefore, to count an interval of 20 seconds, use the following procedure: mov timecon, #0d0h ;enable 24hour mode, count seconds, clear tcen. mov intval, #14h ;load intval with required count interval...in this case 14h = 20 mov timecon, #0d3h ;start tic counting and enable the 8bit intval counter.
aduc845/aduc847/aduc848 rev. b | page 73 of 108 8052- c o mp a t ible on- c hip peripher als this s e c t io n g i ves a b r ief o v er v i e w o f t h e va r i o u s s e co nd a r y p e r i pheral cir c u i ts t h a t a r e a v a i l a b l e t o t h e us er o n -chi p . th e s e f e a t ur es a r e m o s t l y 8052-co m p a t ib le ( w i t h a f e w addi tio n al f e a t ur es) a n d a r e co n t r o l l e d via st a n da r d 8052 s f r b i t def i ni t i o n s. p a r a llel i/o the adu c 845/aduc847/ adu c 848 us e f o ur in p u t/o u t p u t p o r t s t o exc h a n g e da ta wi t h exter n al de vices . i n addi t i o n t o p e r f o r min g g e neral-p u r p os e i/ o , s o me a r e ca p a b l e o f ext e r n al me mor y op e r a t i o ns , w h i l e ot he r s are m u lt i p l e x e d w i t h a l te r n a t e fun c ti o n s f o r th e pe ri ph e r al fun c ti o n s a v a i la b l e o n - c hi p . i n g e n e ral , w h en a p e r i p h eral is ena b led , t h a t p i n c a nn ot b e us ed as a genera l-p u r p os e i/o pin. po r t 0 p o r t 0 is a n 8-b i t o p en -drain b i dir e c t io na l i/o p o r t t h a t is dir e c t l y co n t r o l l ed via t h e p o r t 0 s f r (80h). p o r t 0 is als o th e m u l t i p lexe d lo w - o r der addr ess and da t a b u s d u r i n g acce ss es to ext e r n al da t a mem o r y . f i gur e 48 sh o w s a typ i cal b i t la tc h an d i/o b u f f er f o r a p o r t 0 p i n. th e b i t la t c h (o n e b i t i n t h e p o r t s s f r) is r e p r es en te d as a t y p e d f l i p -f lo p , w h ich clo c ks i n a v a l u e f r o m t h e in t e r n a l b u s i n re sp ons e to a w r i t e to l a tc h s i g n a l f r om t h e c p u . t h e q output of t h e f l ip - f l o p i s pl a c e d on t h e i n te r n a l bu s i n r e s p o n s e t o a r e ad l a t c h sig n al f r o m the cp u . th e l e v e l o f t h e p o r t p i n i t s e lf is p l aced on t h e in t e r n al b u s in r e s p o n s e t o a r e ad p i n sig n al f r o m th e cpu . s o m e in s t r u c t io n s tha t r e ad a p o r t a c t i v a te t h e re a d l a tch s i g n a l , a nd ot he rs a c t i v a te t h e re a d pi n sig n al . s e e t h e re ad-m o d if y- w r i t e i n s t r u c t ion s s e c t ion fo r det a i l s. control read latch internal bus write to latch read pin d cl q q latch dv dd addr/data p0.x pin 04741-048 f i g u re 48. p o r t 0 b i t latc h a n d i/o buf f er a s sho w n in f i g u r e 48, th e ou t p u t dr i v ers o f p o r t 0 p i n s a r e s w itch abl e to an i n te r n a l a ddr an d a ddr / d a t a b u s b y an i n t e rnal co n t r o l si gn al f o r use i n ext e rn al m e m o r y a c ces s es. d u r i n g ext e r n al m e m o r y acces s es, t h e p0 s f r has 1s wr i t t e n t o i t ; t h er efo r e , al l i t s b i t la t c h e s b e co m e 1. w h e n acces s in g ext e r n al mem o r y , the co n t r o l sig n al in f i gur e 4 8 g o es hig h , enabli n g p u sh-pu l l op era t i o n o f t h e out p u t pi n f r o m t h e i n t e r n al addr es s o r da t a b u s (ad d r/ d a t a li n e ). ther efo r e , n o ext e r n al p u l l -u ps a r e r e q u ir ed o n p o r t 0 f o r i t t o acces s ext e r n al m e m o r y . i n g e n e r a l - p u rp o s e i / o p o rt m o d e , p o rt 0 p i n s th a t h a v e 1 s w r i t t e n t o t h em vi a t h e p o r t 0 s f r a r e co n f i g ur ed a s o p en -d ra in a n d , t h er ef o r e , f l o a t. i n this s t a t e , p o r t 0 p i n s can b e us ed as h i g h im pe da n c e in p u t s . t h is is r e p r esen t e d in f i gur e 48 b y t h e n a n d ga t e wh ose o u t p u t r e m a i n s h i gh a s l o n g a s th e c o n t r o l sig n al is lo w , t h er eb y dis a b l in g t h e t o p fet . e x ter n al p u l l -u p r e sis t o r s a r e , th er ef o r e , r e q u ir ed when p o r t 0 p i ns a r e us ed as g e n e r a l - p u rp o s e o u t p u t s . p o rt 0 p i n s w i th 0 s w r i t t e n t o th e m dr i v e a l o gi c lo w o u t p u t v o l t a g e (v ol ) and a r e ca p a b l e o f s i nk i n g 1.6 ma. po r t 1 p o r t 1 is als o a n 8-b i t p o r t dir e c t l y co n t r o l l ed via t h e p1 s f r ( 9 0 h ) . p o r t 1 d i g i t a l output c a p a bi l i t y i s not s u pp or te d on t h i s de vic e . p o r t 1 p i n s can b e co nf ig ur e d as dig i t a l i n p u ts o r a n a l o g in p u ts. by (p o w er -o n) def a u l t, t h es e p i n s a r e conf igur e d as a n a l og in p u ts, t h a t is, 1 is wr i t ten t o t h e co r r esp o ndi n g p o r t 1 r e g i s t er b i t. t o c o nf igur e a n y o f t h es e p i n s as dig i t a l in p u ts, t h e us er s h o u l d wr i t e a 0 t o t h es e p o r t b i ts t o co nf i g ur e t h e co r r e- sp on d i n g p i n as a hig h i m p e dance dig i t a l in p u t. th e s e p i n s a l s o ha v e va r i o u s s e c o nda r y f u n c tion s aside f r o m t h eir a n alog in p u t ca p a b i li ty , as de s c r i b e d in t a b l e 46. t a bl e 46. p o r t 1 al t e r n a t e f u nc ti o n s p i n no . a l t e rna t e f u nc tion p1.2 refin2+ (s ec ond r e f e r e nc e inpu t, + v e ) p1.3 refin2? (s ec ond r e f e r e nc e inpu t, Cv e ) p1.6 iex c 1 (200 a ex cita tion cur r e n t sour c e ) p1.7 iex c 2 (200 a ex cita tion cur r e n t sour c e ) read latch internal bus write to latch read pin d cl q q latch p1.x pin to adc 04741-068 f i g u re 49. p o r t 1 b i t latc h a n d i/o buf f er po r t 2 p o r t 2 is a b i d i r e c t io na l p o r t w i t h i n t e r n a l p u l l - u p r e sist o r s dir e c t l y co n t r o l l e d v i a t h e p2 s f r . p o r t 2 als o emi t s t h e mi ddle - a nd hig h -o r d er addr ess b y tes d u r i n g access es to t h e 24- b i t ext e r n al da t a mem o r y s p ace . i n g e n e r a l - p u rp o s e i / o p o rt m o d e , p o rt 2 p i n s th a t h a v e 1 s w r it te n to t h e m are pu l l e d h i g h b y t h e i n te r n a l pu l l - u p s a s s h o w n in f i gur e 50 a n d , in tha t s t a t e , can be us e d as in p u ts . a s i n pu t s , p o r t 2 pi ns pu l l e d e x te r n a l l y l o w s o u r c e c u r r e n t b e c a u s e o f th e in ter n al p u l l -u p r e sis t o r s. p o r t 2 p i n s wi t h 0s wr i t t e n t o th e m dr iv e a lo g i c lo w o u t p u t vol t a g e (v ol ) an d a r e ca p a b l e o f sinkin g 1.6 ma.
aduc845/aduc847/aduc848 rev. b | page 74 of 108 p2.5 a nd p2.6 c a n als o b e us e d as pwm o u t p u t s, while p2.7 can ac t as a n a l t e r n a t e pw m clo c k s o ur ce. w h e n s e l e c t e d as t h e pwm o u t p u t s, t h e y o v er wr i t e an ythin g wr i t t e n t o p2.5 o r p2.6. t a bl e 47. p o r t 2 al t e r n a t e f u nc ti o n s p i n no . a l t e rna t e f u nc tion p2.0 scl o ck f o r spi p2.1 mosi f o r spi p2.2 miso f o r spi p2.3 ss and t 2 clock input p2.4 t2ex alt e rna t e c o n t r o l f o r t2 p2.5 pwm0 outpu t p2.6 pwm1 outpu t p2.7 pwmclk control read latch internal bus write to latch read pin d cl q latch dv dd addr p2.x pin dv dd internal pull-up q 04741-069 read latch internal bus write to latch read pin d cl q latch dv dd p3.x pin internal pull-up alternate output function alternate input function q 04741-071 f i g u re 51. p o r t 3 b i t latc h a n d i/o buf f er r e a d -mo d if y- w r it e inst ruc t i o ns s o m e 8051 in s t r u c t io n s r e ad t h e la t c h w h ile o t hers r e ad t h e p i n. the ins t r u c t io ns t h a t r e ad t h e l a t c h r a t h er t h an t h e pin s a r e t h e o n es t h a t r e ad a val u e , p o s s i b l y cha n g e i t , an d re wr i t e i t t o t h e la t c h. t h e s e a r e ca l l e d r e a d - m o d if y - wr i t e in st r u c t io n s , w h ich a r e l i s t ed i n t a b l e 49. w h en t h e d e s t i n a t i o n o p era n d i s a po r t o r a po rt b i t , th e s e i n s t ru ct i o n s r e a d th e la t c h r a th e r t h a n th e p i n . t a bl e 49. r e a d - m o d if y-w r it e instr u c t i o ns instruc t ion description anl l o g i cal and , f o r example , anl p1, a orl l o g i cal or, f o r example , orl p2, a xrl l o g i cal ex - o r, f o r example , xrl p3, a jbc jump if bit = 1 and clear bit, f o r examp l e , j b c p1.1, label cpl c o mplemen t bit, f o r example , c pl p3.0 inc i n cr emen t, f o r e x ample , inc p2 dec d e cr emen t, f o r examp l e , dec p2 djnz d e cr emen t and jump if not z e r o , f o r examp l e , djnz p3, label mov p x .y , c 1 m o v e c a rr y t o bit y of p o r t x clr p x .y 1 clear bit y of p o r t x se tb p x .y 1 set bit y of p o r t x __ __ __ __ __ __ __ __ __ __ __ __ __ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ 1 t h ese i n st ruc t i on s r e a d t h e po r t b y t e (a ll 8 bi t s ) , m o di fy t h e a d d r e sse d bi t , and wr it e the ne w b y t e back t o the l a tch. re ad- m o d if y- w r i t e i n s t r u c t io n s a r e dir e c t e d t o t h e la t c h ra t h er t h a n t o t h e pin to a v o i d a p o s s ible misin t er p r et a t io n o f t h e v o l t a g e le ve l o f a p i n. f o r exa m p l e , a p o r t p i n mig h t be us e d to dr i v e t h e b a s e of a t r a n sis t o r . w h e n 1 is wr i t t e n t o t h e b i t, t h e t r ans i stor i s tu r n e d on . i f t h e c p u re a d s t h e s a me p o r t bit a t t h e p i n ra th e r th a n th e la t c h , i t r e a d s th e ba se v o l t a g e o f th e t r a n sist o r a nd i n t e r p r e ts i t as l o g i c 0. re ad in g t h e la t c h ra t h er t h a n t h e pin r e t u r n s t h e co r r e c t val u e o f 1. f i g u re 50. p o r t 2 b i t latc h a n d i/o buf f er po r t 3 p o r t 3 is a b i dir e c t io nal p o r t wi th in t e r n al p u l l -u ps dir e c t l y co n t r o l l ed via t h e p3 s f r (b0 h ). p o r t 3 p i n s t h a t ha v e 1s w r it te n to t h e m are pu l l e d h i g h b y t h e i n te r n a l pu l l - u p s and, i n tha t sta t e , can b e us ed as in p u ts . a s in p u ts, p o r t 3 p i n s p u l l ed ext e r n al l y lo w s o ur ce c u r r en t b e ca us e o f t h e in ter n al p u l l -u ps. p o r t 3 p i n s wi t h 0s wr i t t e n t o t h em dr i v e a log i c lo w o u t p u t vol t age ( v ol ) and a r e ca p a b l e o f sinki n g 4 ma. p o r t 3 p i n s als o ha ve va r i o u s s e c o nda r y f u n c t i on s as des c r i b e d in t a b l e 48. t h e a l te r n ate f u nc t i ons of p o r t 3 pi ns c a n b e a c t i v a te d on ly i f t h e co r r esp o n d in g b i t la t c h in t h e p3 s f r co n t ains a 1. o t h e r w is e, th e po r t p i n r e m a i n s a t 0. t a bl e 48. p o r t 3 al t e r n a t e f u nc ti o n s p i n no . a l t e rna t e f u nc tion p3.0 rxd (u ar t inpu t pin, or serial d a ta i/o in m o de 0) p 3 . 1 t x d (u a r t out p ut pi n, or s e r i al c l oc k output in m o de 0) p3.2 int0 (ex t ernal i n t e rr upt 0) p3.3 int1 (ex t ernal i n t e rr upt 1) p3.4 t0 ( t imer/c o un ter 0 ex ter n al input) p3.5 t1 ( t imer/c o un ter 1 ex ter n al input) p3.6 wr (ex t er nal da ta memor y wr ite str obe) p3.7 rd (ex t ernal da ta memor y r e ad s t r obe)
aduc845/aduc847/aduc848 rev. b | page 75 of 108 timers/counters the aduc845/aduc847/ aduc848 have three 16-bit timer/ counters: timer 0, timer 1, and timer 2. the timer/counter hardware is included on-chip to relieve the processor core of the overhead inherent in implementing timer/counter functionality in software. each timer/counter consists of two 8-bit registers: thx and tlx (x = 0, 1, or 2). all three can be configured to operate either as timers or as event counters. when functioning as a timer, the tlx register is incremented every machine cycle. thus, one can think of it as counting machine cycles. because a machine cycle on a single-cycle core consists of one core clock period, the maximum count rate is the core clock frequency. when functioning as a counter, the tlx register is incremented by a 1-to-0 transition at its corresponding external input pin: t0, t1, or t2. when the samples show a high in one cycle and a low in the next cycle, the count is incremented. because it takes two machine cycles (two core clock periods) to recognize a 1-to-0 transition, the maximum count rate is half the core clock frequency. there are no restrictions on the duty cycle of the external input signal, but, to ensure that a given level is sampled at least once before it changes, it must be held for a minimum of one full machine cycle. user configuration and control of all timer operating modes is achieved via three sfrs: tmod, tcon control and configuration for timers 0 and 1. t2con control and configuration for timer 2. tmodtimer/counter 0 and 1 mode register sfr address: 89h power-on default: 00h bit addressable: no table 50. tmod sfr bit designation bit no. name description 7 gate timer 1 gating control. set by software to enable timer/counter 1 only while the int1 pin is high and the tr1 control is set. cleared by software to enable timer 1 whenever the tr1control bit is set. 6 c/t timer 1 timer or counter select bit. set by software to select counter operation (input from t1 pin). cleared by software to select the timer ope ration (input from internal system clock). timer 1 mode select bits. m1 m0 description 0 0 th1 operates as an 8-bit timer/coun ter. tl1 serves as 5-bit prescaler. 0 1 16-bit timer/counter. th1 and tl1 are cascaded; there is no prescaler. 1 0 8-bit autoreload timer/counter. th1 holds a value th at is to be reloaded into tl1 each time it overflows. 5, 4 m1, m0 1 1 timer/counter 1 stopped. 3 gate timer 0 gating control. set by software to enable timer/counter 0 only while the int0 pin is high and the tr0 control bit is set. cleared by software to enable timer 0 whenever the tr0 control bit is set. 2 c/t timer 0 timer or counter select bit. set by software to the select counter operation (input from t0 pin). cleared by software to the select timer operation (input from internal system clock). timer 0 mode select bits. m1 m0 description 0 0 th0 operates as an 8-bit timer/counter. tl0 serves as a 5-bit prescaler. 0 1 16-bit timer/counter. th0 and tl0 are cascaded; there is no prescaler. 1 0 8-bit autoreload timer/counter. th0 holds a value th at is to be reloaded into tl0 each time it overflows. 1, 0 m1, m0 1 1 tl0 is an 8-bit timer/counter controlled by the standard timer 0 control bits. th0 is an 8-bit timer only, controlled by timer 1 control bits.
aduc845/aduc847/aduc848 rev. b | page 76 of 108 tcontimer/counter 0 and 1 control register sfr address: 88h power-on default: 00h bit addressable: yes table 51. tcon sfr bit designations bit no. name description 7 tf1 timer 1 overflow flag. set by hardware on a timer/counter 1 overflow. cleared by hardware when the program counter (pc) vectors to the interrupt service routine. 6 tr1 timer 1 run control bit. set by the user to turn on timer/counter 1. cleared by the user to turn off timer/counter 1. 5 tf0 timer 0 overflow flag. set by hardware on a timer/counter 0 overflow. cleared by hardware when the pc vectors to the interrupt service routine. 4 tr0 timer 0 run control bit. set by the user to turn on timer/counter 0. cleared by the user to turn off timer/counter 0. 3 ie1 1 external interrupt 1 ( int1 ) flag. set by hardware by a falling edge or by a zero level applied to the external interrupt pin, int1 , depending on the state of bit it1. cleared by hardware when the pc vectors to the interrupt service routine only if the interrupt was transition- activated. if level-activated, the external requesting source controls the request flag rather than the on-chip hardware. 2 it1 1 external interrupt 1 (ie1) trigger type. set by software to specify edge-sensitive detection, that is, 1-to-0 transition. cleared by software to specify level-sensitive detection, that is, zero level. 1 ie0 1 external interrupt 0 ( int0 ) flag. set by hardware by a falling edge or by a zero level being applied to the external interrupt pin, int0 , depending on the statue of bit it0. cleared by hardware when the pc vectors to the interrupt service routine only if the interrupt was transition- activated. if level-activated, the external requesting source controls the request flag rather than the on-chip hardware. 0 it0 1 external interrupt 0 (ie0) trigger type. set by software to specify edge-sensitive detection, that is, 1-to-0 transition. cleared by software to specify level-sensitive detection, that is, zero level. ___________________________________________ 1 these bits are not used to control timer/counters 0 and 1, but are used instead to control and monitor the external int0 and int1 interrupt pins. timer/counter 0 and 1 data registers each timer consists of two 8-bit registers. these can be used as independent registers or combined into a single 16-bit registe r, depending on the timers mode configuration. th0 and tl0 timer 0 high and low bytes. sfr address: 8ch and 8ah, respectively. power-on default: 00h and 00h, respectively. th1 and tl1 timer 1 high and low bytes. sfr address: 8dh and 8bh, respectively. power-on default: 00h and 00h, respectively.
aduc845/aduc847/aduc848 rev. b | page 77 of 108 t i m e r/ cou n te r 0 a n d 1 o p er a t ing mo des this s e c t io n de s c r i b e s t h e o p era t in g m o des fo r t i m e r/ c o un t e rs 0 a nd 1. u n less o t h e r w is e n o te d, t h e s e m o des o f o p er a t io n a r e t h e s a me for b o t h t i me r 0 a n d t i me r 1 . m o de 0 (13-b i t t i me r/c o un t e r) m o de 0 co nf igu r es a n 8-b i t timer/co un ter . f i gu r e 52 s h o w s m o de 0 o p er a t i o n. n o te t h a t t h e divi de- b y - 12 p r es ca ler is n o t p r es en t o n t h e s i n g le -c ycle co r e . 04741- 049 core clk 1 control p3.4/t0 gate p3.2/ in t 0 tr0 tf0 tl0 (5 bits) th0 (8 bits) interrupt c/ t = 0 c/ t = 1 notes 1. the core clock is the output of the pll (see the on-chip pll section) f i g u re 52. ti m e r/ count e r 0, m o de 0 i n t h i s mo de, t h e t i m e r r e g i s t er is co nf igur e d as a 13-b i t r e g i st er . a s t h e co u n t r o l l s o v er f r o m al l 1s t o al l 0s, i t s e ts t h e t i m e r ov e r f l ow f l a g , t f 0 . t f 0 c a n t h e n b e u s e d t o r e q u e s t a n i n te r r upt . t h e c o u n te d i n put i s e n abl e d to t h e t i me r w h e n tr 0 = 1 a n d ei t h er ga te = 0 o r int0 = 1. s e t t in g ga te = 1 allo ws t h e tim e r t o b e co n t r o l l ed b y ext e r n al in p u t int0 to f a c i l i t a te pu l s e - w i d t h m e a s ur em en t s . t r 0 i s a co n t r o l b i t i n t h e s p eci a l fun c tio n r e g i s t er t c on; ga te is in t m od . th e 13-b i t r e g i s t er co n s is ts of al l 8 b i ts o f th0 a nd t h e lo w e r 5 b i ts o f tl0. the u p p e r 3 b i ts o f tl0 a r e i ndeter m ina t e and sh ou ld b e ig n o r e d . s e t t in g t h e r u n f l a g (t r0) do es n o t c l ea r t h e r e gis t er s. m o de 1 (16-b i t t i me r/c o un t e r) m o de 1 is t h e s a m e as m o de 0 excep t tha t t h e m o de 1 tim e r r e g i s t er r u n s wi th al l 16 b i ts. m o de 1 is sh o w n in f i gur e 53. core clk 1 control p3.4/t0 gate tr0 tf0 tl0 (8 bits) th0 (8 bits) interrupt 04741- 050 0 p3.2/ i n t c/ t = 0 c/ t = 1 notes 1. the core clock is the output of the pll (see the on-chip pll section) f i g u re 53. ti m e r/ count e r 0, m o de 1 m o de 2 (8-b i t t i me r/c o un t e r w i th a u t o r e lo ad ) m o de 2 co nf igu r es t h e t i m e r r e g i s t er as a n 8- b i t co un t e r ( t l0) w i t h a u tom a t i c rel o a d a s s h ow n i n fi g u re 5 4 . o v e r f l o w f r om tl0 n o t o n l y s e ts tf0, b u t als o r e lo ads tl0 wi t h t h e co n t en ts of th0, w h ich is pr es et b y s o f t wa re . th e r e lo ad le a v es th0 un c h an g e d . control tf0 tl0 (8 bits) interrupt reload th0 (8 bits) core clk 1 p3.4/t0 gate tr0 0 04741-051 p3.2/ in t c/ t = 0 c/ t = 1 notes 1. the core clock is the output of the pll (see the on-chip pll section) f i g u re 54. ti m e r/ count e r 0, m o de 2 mo de 3 ( t w o 8 - bit t i me r/ co u n ters) m o de 3 has dif f er en t ef f e c t s o n t i m e r 0 a nd t i m e r 1. t i mer 1 in m o de 3 sim p l y h o lds i t s co un t. the ef fe c t is th e s a m e as s e t t in g tr1 = 0. t i m e r 0 in m o de 3 es t a b l ish e s tl0 and th0 as tw o s e p a ra t e co u n te rs. this co nf igu r a t io n is sho w n in f i gur e 55. tl0 us es t h e t i m e r 0 c o n t r o l bi ts c/ t , ga t e , tr0, int0 , a nd tf0. th0 is lo ck ed in t o a t i m e r f u n c tion (co u n t in g machin e c y cles) a n d t a k e s o v er t h e us e o f tr1 and tf1 f r o m t i m e r 1. ther ef o r e , th0 th en co n t r o ls t h e t i m e r 1 in t e r r u p t. m o de 3 is p r o v id e d fo r a p plic a t io n s r e quir in g an ext r a 8-b i t t i m e r o r co un t e r . w h en t i m e r 0 is in m o de 3, t i m e r 1 can be t u r n ed on an d o f f b y sw i t ch in g i t o u t o f a nd i n to i t s o w n m o de 3, o r i t ca n st i l l b e us e d b y t h e s e r i a l in t e r f ace as a b a ud ra t e ge n e r a t o r . i n fac t , i t ca n b e us e d i n an y a p pli c a t io n no t r e q u ir in g an in t e r r u p t f r o m ti m e r 1 it s e l f . control core clk/12 tf0 tl0 (8 bits) interrupt core clk 1 p3.4/t0 gate tr0 tf1 th0 (8 bits) interrupt core clk/12 tr1 04741- 052 0 p3.2/ in t c/ t = 0 c/ t = 1 notes 1. the core clock is the output of the pll (see the on-chip pll section) f i g u re 55. ti m e r/ count e r 0, m o de 3
aduc845/aduc847/aduc848 rev. b | page 78 of 108 t2contimer/counter 2 control register sfr address: c8h power-on default: 00h bit addressable: yes table 52. t2con sfr bit designations bit no. name description 7 tf2 timer 2 overflow flag. set by hardware on a timer 2 overflow. tf2 cannot be set when either rclk = 1 or tclk = 1. cleared by user software. 6 exf2 timer 2 external flag. set by hardware when either a capture or reload is ca used by a negative transition on t2ex and exen2 = 1. cleared by user software. 5 rclk receive clock enable bit. set by the user to enable the serial port to use timer 2 overflow pulses for its receive clock in serial port modes 1 and 3. cleared by the user to enable timer 1 overflow to be used for the receive clock. 4 tclk transmit clock enable bit. set by the user to enable the se rial port to use timer 2 overflow pulses for its transmit clock in serial port modes 1 and 3. cleared by the user to enable timer 1 over flow to be used for the transmit clock. 3 exen2 timer 2 external enable flag. set by the user to enable a capture or reload to occur as a re sult of a negative transition on t2ex if timer 2 is not being used to clock the serial port. cleared by the user for timer 2 to ignore events at t2ex. 2 tr2 timer 2 start/stop control bit. set by the user to start timer 2. cleared by the user to stop timer 2. 1 cnt2 timer 2 timer or counter function select bit. set by the user to select the counter function (input from external t2 pin). cleared by the user to select the timer function (input from on-chip core clock). 0 cap2 timer 2 capture/reload select bit. set by the user to enable captures on ne gative transitions at t2ex if exen2 = 1. cleared by the user to enable autoreloads with timer 2 ov erflows or negative transitions at t2ex when exen2 = 1. when either rclk = 1 or tclk = 1, this bit is ignored and the timer is forced to autoreload on timer 2 overflow. timer/counter 2 data registers timer/counter 2 also has two pairs of 8-bit data registers associated with it. these are used as both timer data registers and as timer capture/reload registers. th2 and tl2 timer 2 data high byte and low byte. sfr address: cdh and cch respectively. power-on default: 00h and 00h, respectively. rcap2h and rcap2l timer 2 capture/reload byte and low byte. sfr address: cbh and cah, respectively. power-on default: 00h and 00h, respectively.
aduc845/aduc847/aduc848 rev. b | page 79 of 108 t i m e r/ cou n te r 2 o p er a t ing m o des the fol l o w in g s e c t io n s de s c r i b e t h e op era t in g m o des fo r t i m e r/ c o un t e r 2. the o p era t ing m o des a r e s e l e c t e d b y b i ts i n t h e t2c o n s f r as sh o w n in t a b l e 53. t a bl e 53. t2c o n o p e r a t in g m o des r c lk (or) t c lk c a p2 tr2 mode 0 0 1 16-bit a u tor e load 0 1 1 16-bit c a ptur e 1 x 1 baud r a te x x 0 o ff 16-b i t a u t o r e l o ad m o d e a u torel o a d mo d e h a s t w o opt i ons t h a t are s e l e c t e d b y bit exen2 in t2c o n. i f exe n 2 = 0, wh en t i m e r 2 r o lls o v er , i t n o t o n ly s e ts tf2 b u t a l s o c a us e s t h e t i m e r 2 r e g i st ers t o b e r e lo ade d wi t h t h e 16- b i t va l u e i n r e g i s t ers r c a p 2l a nd r c ap2h, w h ich a r e p r es et b y s o f t wa r e . i f e x e n 2 = 1, t i m e r 2 s t i l l p e r f o r m s t h e a b o v e , b u t wi t h t h e adde d fe a t ur e t h a t a 1-t o - 0 tra n si ti o n a t e x t e rn al i n p u t t 2 ex also tri g g e r s t h e 16-b i t r e loa d a nd s e ts exf 2 . a u to r e lo ad m o de is sh o w n i n f i gur e 56. 16-b i t c a p t ur e m o de ca p t ur e m o d e h a s t w o o p ti o n s th a t a r e s e lect e d b y b i t ex en 2 in t2con. i f e x en2 = 0, t i mer 2 is a 16-b i t tim e r o r co un t e r t h at , u p o n ov e r f l ow i n g , s e t s bi t t f 2 , t h e t i m e r 2 ov e r f l ow bit , which can b e us ed t o g e n e ra te an in t e r r u p t. i f e x en2 = 1, t i m e r 2 st i l l p e r f o r m s t h e ab o v e, b u t a l-t o -0 t r an si t i o n on ext e r n al in p u t t2ex ca us es t h e c u r r en t val u e in t h e t i m e r 2 re g i ste r s , t l 2 a nd th 2 , to b e c a pt u r e d i n to r e g i ste r s rc a p 2 l a n d r c a p 2h , r e s p ecti v e l y . i n ad di ti o n , t h e tra n si ti o n a t t 2 ex ca us es bi t exf 2 in t2c o n to b e s e t, and exf 2 , li k e tf 2, c a n g e n e ra t e an in t e r r u p t. c a p t ur e m o de is sh o w n in f i gur e 57. the b a u d r a te ge ne r a tor mo de i s s e l e c t e d b y rc l k = 1 and / or t c lk = 1. i n ei t h er cas e , if t i m e r 2 is us ed t o g e n e ra t e t h e ba ud ra t e , t h e tf2 in t e r r u p t f l a g do es n o t o c c u r . th er efo r e , t i mer 2 in t e r r u p ts do n o t o c c u r , s o they do n o t ha ve t o be dis a b l e d . i n this mo de , t h e e x f2 f l a g c a n, h o we v e r , s t i l l ca us e in ter r u p ts, w h i c h c a n b e u s e d a s a t h i r d e x te r n a l i n te r r upt . b a u d r a te ge n e ra tio n i s des c r i b e d as p a r t o f t h e u a r t s e r i al p o r t op era t io n i n t h e fol l o w in g s e c t io n. core clk 1 t2 pin tr2 control tl2 (8 bits) th2 (8 bits) reload tf2 exf2 timer interrupt exen2 control transition detector t2ex pin rcap2l rcap2h * 04741- 053 c/ t2 = 0 c/ t2 = 1 notes 1. the core clock is the output of the pll (see the on-chip pll section) f i g u re 56. ti m e r/ count e r 2, 16-b i t au t o rel oad m o d e tf2 core clk 1 t2 pin tr2 control tl2 (8 bits) th2 (8 bits) capture exf2 timer interrupt exen2 control transition detector t2ex pin rcap2l rcap2h * 04741-054 c/ t2 = 0 c/ t2 = 1 notes 1. the core clock is the output of the pll (see the on-chip pll section) f i g u re 57. ti m e r/ count e r 2, 16-b i t ca pt ur e m o de
aduc845/aduc847/aduc848 rev. b | page 80 of 108 uart serial interface the serial port is full duplex, meaning that it can transmit and receive simultaneously. it is also receive buffered, meaning that it can begin receiving a second byte before a previously received byte is read from the receive register. however, if the first byte is still not read by the time reception of the second byte is complete, the first byte is lost. the physical interface to the serial data network is via pins rxd(p3.0) and txd(p3.1), while the sfr interface to the uart comprises sbuf and scon, as described below. sbuf sfr both the serial port receive and transmit registers are accessed through the sbuf sfr (sfr address = 99h). writing to sbuf loads the transmit register, and reading sbuf accesses a physically separate receive register. scon uartserial port control register sfr address: 98h power-on default: 00h bit addressable: yes table 54. scon sfr bit designations bit no. name description uart serial mode select bits. these bits select the serial port operating mode as follows: sm0 sm1 selected operating mode. 0 0 mode 0: shift register, fixed baud rate (core_clk/2). 0 1 mode 1: 8-bit uart, variable baud rate. 1 0 mode 2: 9-bit uart, fixed baud rate (core_clk/32) or (core_clk/16). 7, 6 sm0, sm1 1 1 mode 3: 9-bit uart, variable baud rate. 5 sm2 multiprocessor communication enable bit. enables multiprocessor communication in modes 2 and 3. in mode 0, sm2 should be cleared. in mode 1, if sm2 is set, ri is not activated if a valid stop bit was not received. if sm2 is cl eared, ri is set as soon as the byte of data is received. in modes 2 or 3, if sm2 is set, ri is not activa ted if the received ninth data bit in rb8 is 0. if sm2 is cleared, ri is set as soon as the byte of data is received. 4 ren serial port receive enable bit. set by user software to enable serial port reception. 3 tb8 serial port transmit (bit 9). the data loaded into tb8 is the ninth data bit transmitted in modes 2 and 3. cleared by user software to disable serial port reception. 2 rb8 serial port receiver bit 9. the ninth data bit received in modes 2 and 3 is latched in to rb8. for mode 1, the stop bit is latched into rb8. 1 ti serial port transmit interrupt flag. set by hardware at the end of the eighth bit in mode 0, or at the beginning of the stop bit in modes 1, 2, and 3. ti must be cleared by user software. 0 ri serial port receive interrupt flag. set by hardware at the end of the eighth bit in mode 0, or halfway through the stop bit in modes 1, 2, and 3. ri must be cleared by software. sbufuart serial port data register sfr address: 99h power-on default: 00h bit addressable: no
aduc845/aduc847/aduc848 rev. b | page 81 of 108 mo d e 0 ( 8 - b i t s h i f t r e g i s t e r mo d e ) m o de 0 is s e lec t ed b y c l ea r i n g b o th t h e s m 0 and s m 1 b i ts in t h e s f r sc o n . s e r i al da t a en t e rs and exi t s t h r o ug h rxd . txd o u t p uts t h e shif t clo c k. ei g h t da t a b i ts a r e t r a n s m i t t e d o r r e cei v e d . t r a n s m issio n is i n i t i a t e d b y a n y in st r u c t io n t h a t wr i t es t o s b uf . th e da t a is s h if t e d o u t o f t h e rxd l i n e . the 8 b i ts a r e t r a n smi t t e d w i t h t h e le ast sig n i f ica n t b i t (lsb) f i rst. re ce p t io n is ini t ia t e d w h e n t h e r e cei v e ena b l e b i t (ren) is 1 a nd t h e r e cei ve in t e r r u p t b i t ( r i) is 0. w h en ri is c l ea r e d , t h e da t a is clo c ke d i n t o t h e rxd l i ne , a nd t h e clo c k p u ls es a r e output f r om t h e t x d l i ne a s s h ow n i n f i g u re 5 8 . rxd (data out) txd (shift clock) data bit 0 data bit 1 data bit 6 data bit 7 04741-055 f i g u re 58. 8-b i t sh if t r e g i s t er m o de m o de 1 (8-b i t u a r t , v a ri a b le ba u d r a t e ) m o de 1 is s e le c t e d b y cle a r i n g sm0 a nd s e t t i n g s m 1. e a ch da t a b y t e (l s b f i r s t ) i s p r eced ed b y a s t a r t b i t (0) a n d f o ll o w ed b y a stop bit ( 1 ) . t h e r e f ore, 1 0 bit s are t r ans m itte d o n t x d or are r e cei v ed o n rxd . th e ba ud ra te is set b y t h e t i m e r 1 o r t i m e r 2 o v er f l o w ra t e , or a co m b in a t ion o f t h e tw o (o n e fo r t r a n smissio n a nd t h e o t h e r fo r r e cep t io n). t r a n smission is ini t i a t e d b y wr i t in g t o s b uf . t h e wr i t e t o sb uf sig n al als o lo ads a 1 (s t o p b i t) in t o t h e 9t h b i t p o si tio n o f the tra n sm i t s h i f t r e gi s t e r . th e da ta i s o u t p u t b i t - b y -b i t un til t h e s t o p b i t a p p e a r s o n txd and t h e tra n smi t in t e r r u p t f l a g (ti) is a u t o ma tic a l l y s e t as sh o w n in f i gur e 59. txd ti ( s con.1) start bit d0 d1 d2 d3 d4 d5 d6 d7 stop bit set interrupt i . e ., ready for more data 04741-056 f i g u re 59. 8-b i t v a ri abl e b a ud r a te re ce p t io n is ini t ia t e d w h e n a 1- t o -0 t r a n si t i on i s det e c t e d on r x d . a s su mi ng t h a t a v a l i d st ar t b i t is de te c t e d , char ac te r r e cep t io n con t i n ues. t h e st a r t b i t is sk i p p e d and t h e 8 da t a b i ts a r e clo c k e d i n t o t h e s e r i al p o r t shif t r e g i s t er . w h e n al l 8 b i ts h a v e been c l oc k e d in , t h e f o ll o w i n g ev e n ts occur : ? th e 8 b i t s in t h e r e ce i v e s h i f t r e g i s t e r a r e l a t c h e d in t o s b u f . ? the 9t h b i t (st o p b i t) is clo c k e d in t o rb8 in s c on. ? the r e cei v er i n ter r u p t f l a g (ri) is s e t. a l l o f th e f o ll o w i n g c o n d i t i o n s m u s t b e m e t a t th e ti m e th e fi n a l shif t p u ls e is ge n e ra t e d: ? ri = 0 ? ei t h er s m 2 = 0 o r s m 2 = 1 ? re cei v e d st o p b i t = 1 i f a n y o f t h es e c o n d i t io ns is no t m e t, t h e r e ce i v e d f r a m e is ir r e t r ie vab l y lost, an d ri is n o t s e t. m o d e 2 (9-b it u a r t w i th fixe d ba u d r a t e ) m o de 2 is s e le c t e d b y s e tt in g sm0 a nd cle a r i ng s m 1. i n t h is m o de , t h e u a r t o p era t es in 9- b i t m o de w i t h a f i xe d b a ud ra t e . the ba u d ra te is f i xed a t c o r e _ c l k /64 b y def a u l t, al t h o u g h b y s e t t in g t h e s m od b i t in pc on, t h e f r e q ue n c y ca n b e doub le d to c o re _ c l k / 3 2 . e l e v e n b i t s are t r ans m it te d or re c e ive d : a st ar t b i t (0), 8 da t a b i ts, a p r og ra mma b l e 9t h b i t, and a st o p b i t (1). the 9th b i t is mos t o f t e n us ed as a p a r i ty b i t, al t h o u g h i t can b e us ed f o r a n ythin g , in cl udin g a nin t h da ta b i t if r e q u ir ed . t o tra n sm i t , t h e 8 d a ta b i ts m u st be w r i t t e n i n t o s b u f . th e nin t h b i t m u st b e wr i t ten t o tb 8 in sc on. w h en t r a n smission is ini t i a t e d , t h e 8 d a t a b i ts (f r o m s b uf) a r e lo ade d in t o t h e tra n sm i t s h i f t r e gi s t e r (l s b f i r s t). t h e co n t e n ts o f t b 8 a r e lo ade d in t o t h e 9th b i t p o si t i o n o f th e tra n smi t s h if t r e g i st er . the t r a n smis sion s t a r ts a t t h e next vali d b a u d ra t e clo c k. th e t i f l ag i s s e t a s s o on a s t h e stop bit a p p e ar s on t x d . re ce p t io n fo r m o de 2 is sim i l a r to t h a t o f m o de 1. t h e 8 d a t a b y t e s a r e i n p u t a t rxd (ls b f i rst) a nd lo ade d o n t o t h e r e cei ve s h i f t r e gi s t e r . w h en all 8 b i t s ha v e been c l oc k e d i n , t h e f o ll o w i n g ev en ts occur : ? th e 8 b i t s in t h e r e ce i v e s h i f t r e g i s t e r a r e l a t c h e d in t o s b u f . ? th e 9 t h d a t a bi t i s l a tc he d i n to r b 8 i n s c on. ? the r e cei v er in ter r u p t f l a g (ri) is s e t. a l l o f th e f o ll o w i n g c o n d i t i o n s m u s t b e m e t a t th e ti m e th e fi n a l shif t p u ls e is ge n e ra t e d: ? ri = 0 ? ei t h er s m 2 = 0 o r s m 2 = 1 ? re cei v e d st o p b i t = 1 i f a n y o f t h es e c o n d i t io ns is no t m e t, t h e r e ce i v e d f r a m e is ir r e t r ie vab l y lost, an d ri is n o t s e t.
aduc845/aduc847/aduc848 rev. b | page 82 of 108 m o d e 3 (9-b it u a r t w i th v a ri abl e ba u d r a t e ) m o de 3 is s e le c t e d b y s e tt in g b o t h s m 0 and s m 1. i n t h i s m o de, th e 8 0 5 1 u a r t s e ri a l po rt o p e r a t e s i n 9 - b i t m o d e w i t h a v a ri a b l e ba ud ra t e det e r m in ed b y ei t h er t i m e r 1 o r t i mer 2. t h e o p era - tio n o f t h e 9-b i t u a r t is t h e s a m e as f o r m o de 2, b u t t h e ba u d ra t e can be va r i ed as f o r m o de 1. i n a l l fo ur mo d e s, t r a n smissio n is ini t i a t e d b y a n y inst r u c t io n t h a t us es sb uf as a dest ina t io n r e g i st er . re cep t i o n is in i t ia te d i n m o de 0 w h en ri = 0 a n d ren = 1. recep t io n is ini t ia t e d in t h e o t h e r m o des b y t h e i n co min g st a r t b i t if re n = 1. u a r t s e rial p o r t baud r a t e gener a tion m o d e 0 ba u d r a t e g e ner a ti o n the ba u d ra te in m o de 0 is f i xe d: mo d e 0 b a u d r a t e = ? ? ? ? ? ? 12 frequency clock core m o d e 2 ba u d r a t e g e ner a ti o n the b a u d ra te i n m o de 2 dep e n d s on t h e va l u e o f t h e s m o d b i t in t h e p c o n s f r . i f s m o d = 0, th e ba u d ra t e is 1/32 o f th e co r e c l o c k. i f s m o d = 1, th e b a ud ra t e is 1/16 o f th e co r e c l o c k: mo d e 2 b a u d r a t e = 32 2 smod co r e c l o c k f r e q u e n c y m o des 1 a n d 3 ba ud r a t e g e ne ra t i o n the b a u d r a tes i n m o des 1 and 3 a r e de t e r m i n e d b y t h e o ver f l o w ra t e in t i mer 1 o r t i m e r 2, o r in bo th (o n e f o r tra n smi t an d t h e o t h e r f o r r e cei v e). t i m e r 1 g e n e r a te d b a u d r a te s w h en t i m e r 1 is us ed as t h e b a ud ra t e g e n e r a to r , th e b a ud ra tes in m o des 1 an d 3 a r e deter m i n e d b y t h e t i m e r 1 o v er f l o w r a te a nd t h e v a l u e o f s m o d as fol l o w s: m o d e s 1 a n d 3 ba u d ra t e = ti m e r 1 o v e r f l o w r a t e the t i m e r 1 i n ter r u p t sh o u ld b e dis a b l e d i n t h i s a p plic a t ion. t h e tim e r i t s e lf ca n be co n f igur ed f o r ei ther tim e r o r co un t e r o p er a t ion, an d i n an y o f i t s t h r e e r u nnin g m o de s. i n t h e m o st ty p i c a l a p pli c a t i o n, i t is co nf igu r e d fo r t i m e r o p era t io n in a u t o r e lo ad mo de (hig h nib b l e o f t m o d = 0010 b i na r y ). i n tha t c a s e , th e b a ud r a t e i s gi v e n b y th e f o rm ula m odes 1 a n d 3 b a ud ra te = 32 2 smod ) 256 ( 32 2 th1 frequency clock core smod ? t i m e r 2 g e n e r a te d b a u d r a te s b a ud ra t e s ca n al so be g e n e ra t e d b y u s i n g t i m e r 2 . u s in g t i m e r 2 i s s i m i l a r t o u s i n g t i m e r 1 i n th a t th e ti m e r m u s t o v e r f l o w 1 6 tim e s b e f o r e a b i t i s tra n smi t t e d o r r e ce i v ed . b e ca use t i m e r 2 has a 16-b i t a u to r e lo ad mo d e , a wid e r ra n g e o f ba ud ra t e s is pos s i b l e . mo d e s 1 a n d 3 b a u d r a t e = 16 1 ti m e r 2 o v e r f l o w r a t e t h er ef o r e , wh en t i m e r 2 is use d t o g e n e ra t e ba ud ra t e s, t h e t i m e r i n cr e m en ts e v er y tw o clo c k c y cles ra t h er t h a n e v er y co r e machi n e c y cle as b e fo r e . i t i n cr e m e n ts six t i m e s fas t er t h an t i m e r 1, a n d , t h er efo r e , ba ud ra t e s six tim e s faster a r e p o s s i b le . b e ca us e t i m e r 2 has 16-b i t a u to r e lo ad ca p a b i l i ty , v e r y lo w ba u d r a te s are st i l l p o ss ibl e . t i m e r 2 is se lec t ed as t h e ba ud ra t e g e n e ra t o r b y set t in g t h e t c lk and/o r rclk in t2c o n. the ba u d ra t e s f o r tra n smi t a nd r e cei v e ca n b e si m u l t an e o u sly dif f er en t. s e tt in g rcl k a n d / o r t c lk p u ts t i m e r 2 in t o i t s b a ud ra t e g e n e ra t o r m o d e as sh ow n i n fi g u re 6 0 . i n this cas e , t h e ba ud ra t e is g i v e n b y t h e f o r m u l a mo d e s 1 a n d 3 b a u d r a t e = () [] () l rcap h rcap frequency clock core 2 : 2 65536 16 ? core clk 1 t2 pin tr2 control tl2 (8 bits) th2 (8 bits) reload exen2 control t2ex pin t ransition detector exf 2 timer 2 interrupt rcap2l rcap2h timer 2 overflow 2 16 16 rclk tclk rx clock tx clock 0 0 1 1 1 0 smod timer 1 overflow c/ t2 = 0 c/ t2 = 1 04741- 057 notes 1. the core clock is the output of the pll (see the on-chip pll section) f i g u re 60. ti m e r 2, u a rt baud ra tes
aduc845/aduc847/aduc848 rev. b | page 83 of 108 t i m e r 3 g e n e r a te d b a u d r a te s the hi g h i n tege r di v i ders i n a u a r t b l o c k m e an t h a t hig h sp e e d b a u d r a te s are not a l w a y s p o ss ibl e . a l s o , ge ne r a t i ng b a u d ra t e s r e q u ir es t h e excl usi v e us e o f a t i m e r , r e nder in g i t u n us a b l e fo r o t h e r a p plic a t io n s w h en t h e u a r t is r e quire d . t o ad dr ess this p r ob lem, t h e aduc845 /aduc847/ad uc848 ha v e a d e d i ca t e d ba ud ra t e tim e r ( t imer 3) s p ecif ically f o r g e n e ra tin g highl y accura t e ba ud ra t e s. t i mer 3 ca n be use d in s t ead o f t i m e r 1 o r t i mer 2 f o r g e n e ra tin g v e r y accura te hig h s p ee d u a r t ba u d ra tes in cl udin g 11 5200 a nd 230400. t i m e r 3 als o allo ws a m u c h wid e r ra n g e o f ba ud ra t e s t o be o b ta in e d . i n fac t , ev er y desir e d b i t ra t e f r o m 12 b p s t o 393216 b p s ca n be g e n e ra t e d t o wi t h in an er r o r o f 0.8% . t i m e r 3 also f r ees u p th e o t h e r t h r e e t i m e rs, al lo w i n g t h e m t o b e us e d for dif f er en t a p plic a t io n s . a b l o c k d i a g ra m of t i mer 3 is sh o w n i n f i gur e 61 . (1 + t3fd/64) t3 rx/tx clock core clk t3en rx clock tx clock timer 1/timer 2 rx clock fractiona l divider 0 0 1 1 timer 1/timer 2 tx clock 16 2 div 04741-058 f i g u re 61. ti m e r 3, u a rt baud ra te t w o s f rs ( t 3c o n a nd t3fd) a r e us ed t o co n t r o l t i m e r 3. t3c o n is t h e b a ud ra t e co n t r o l s f r , al lo win g t i m e r 3 t o b e u s e d to s e t up t h e u a r t b a u d r a te, a nd to s e t up t h e b i nar y divider (d iv). the a p p r o p r i a t e val u e t o wr i t e to t h e d i v2 -1-0 b i ts can b e calc u l a t e d usin g t h e fol l o w in g fo r m u l a w h er e f co r e is def i n e d i n p l l c o n s f r . n o t e t h a t t h e div val u e m u s t b e r o un de d do w n . di v = ) 2 ( log 16 log ? ? ? ? ? ? ? ? t3fd is t h e f r ac t i o n a l d i v i der r a t i o r e q u ir e d t o achie v e t h e r e q u ir e d b a ud r a t e . th e a p p r o p r i a t e val u e fo r t3fd ca n b e c a l c u l a t e d w i t h t h e fol l o w ing fo r m u l a: t3f d = rate baud frequency clock core div ? ? 64 n o te t h a t t3f d sh o u l d b e r o unde d to t h e ne a r est i n teger . o n c e t h e val u es fo r d i v a nd t3f d a r e calc u l a t e d , t h e ac t u al b a u d r a te c a n b e c a l c u l a t e d wit h t h e fol l o w ing fo r m u l a: ac t u a l b a u d r a t e = ) 64 ( 2 2 1 + ? f o r exa m p l e , t o g e t a b a ud ra t e o f 9600 while op era t in g a t a co r e c l o c k f r eq uen c y o f 1.5725 mh z, tha t is, cd = 3, di v = log(1572 500/(16 9600))/log2 = 3.35 = 3 n o te t h a t t h e d i v re su lt i s rou n d e d d o w n . t3f d = (2 1572500)/(2 3?1 9600) ? 64 = 18 = 12h ther ef o r e , th e ac t u al ba u d ra te is 9588 b p s, whic h g i v e s a n er r o r o f 0.12%. the t3 c o n and t3f d r e g i ster s a r e us e d to con t r o l t i m e r 3. t3c o n C t i m e r 3 cont rol r egi st er s f r a ddr ess: 9eh p o w e r - o n def a u l t: 00h bi t a d dr es s a b l e: n o t a bl e 55. t3c o n s f r b i t de sig n a t i o ns bit no . name description 7 t3ba uden t3u a r t ba ud enabl e . s e t t o enable t imer 3 t o gener a t e the baud r a t e . w h en set, pc on.7, t2c o n.4, a n d t2c o n.5 ar e ig nor e d . c l ear e d to let the baud r a te be generated as per a standar d 8052. 6 not i m plemen ted . w r ite d o n t c a r e . 5 not i m plemen ted . w r ite d o n t c a r e . 4 not i m plemen ted . w r ite d o n t c a r e . 3 not i m plemen ted . w r ite d o n t c a r e . 2, 1, 0 div2, div1, div0 binar y divider div2 div1 div0 0 0 0 binar y divider 0. s ee t a ble 57. 0 0 1 binar y divider 1. s ee t a ble 57. 0 1 0 binar y divider 2. s ee t a ble 57. 0 1 1 binar y divider 3. s ee t a ble 57. 1 0 0 binar y divider 4. s ee t a ble 57. 1 0 1 binar y divider 5. s ee t a ble 57. 1 1 0 binar y divider 6. s ee t a ble 57.
aduc845/aduc847/aduc848 rev. b | page 84 of 108 t3fdtimer 3 fractional divider register see table 57 for values. sfr address: 9dh power-on default: 00h bit addressable: no table 56. t3fd sfr bit designations bit no. name description 7 ---- not implemented. write dont care. 6 ---- not implemented. write dont care. 5 t3fd.5 timer 3 fractional divider bit 5. 4 t3fd.4 timer 3 fractional divider bit 4. 3 t3fd.3 timer 3 fractional divider bit 3. 2 t3fd.2 timer 3 fractional divider bit 2. 1 t3fd.1 timer 3 fractional divider bit 1. 0 t3fd.0 timer 3 fractional divider bit 0. table 57. common baud rates using timer 3 with a 12.58 mhz pll clock ideal baud cd div t3con t3fd % error 230400 0 1 81h 2dh 0.18 115200 0 2 82h 2dh 0.18 115200 1 1 81h 2dh 0.18 57600 0 3 83h 2dh 0.18 57600 1 2 82h 2dh 0.18 57600 2 1 81h 2dh 0.18 38400 0 4 84h 12h 0.12 38400 1 3 83h 12h 0.12 38400 2 2 82h 12h 0.12 38400 3 1 81h 12h 0.12 19200 0 5 85h 12h 0.12 19200 1 4 84h 12h 0.12 19200 2 3 83h 12h 0.12 19200 3 2 82h 12h 0.12 19200 4 1 81h 12h 0.12 9600 0 6 86h 12h 0.12 9600 1 5 85h 12h 0.12 9600 2 4 84h 12h 0.12 9600 3 3 83h 12h 0.12 9600 4 2 82h 12h 0.12 9600 5 1 81h 12h 0.12
aduc845/aduc847/aduc848 rev. b | page 85 of 108 interrupt system the aduc845/aduc847/ad uc848 provide nine interrupt sources with two priority levels. the control and configuration of the interrupt system is carried out through three interrupt-related sfrs: ie interrupt enable register ip interrupt priority register ieip2 secondary interrupt enable register ieinterrupt enable register sfr address: a8h power-on default: 00h bit addressable: yes table 58. ie sfr bit designations bit no. name description 7 ea set by the user to enable all interrupt sources. cleared by the user to disable all interrupt sources. 6 eadc set by the user to enable the adc interrupt. cleared by the user to disable the adc interrupt. 5 et2 set by the user to enable the timer 2 interrupt. cleared by the user to disable the timer 2 interrupt. 4 es set by the user to enable the uart serial port interrupt. cleared by the user to disable the uart serial port interrupt. 3 et1 set by the user to enable the timer 1 interrupt. cleared by the user to disable the timer 1 interrupt. 2 ex1 set by the user to enable external interrupt 1 ( int0 ). cleared by the user to disable external interrupt 1 ( int0 ). 1 et0 set by the user to enable the timer 0 interrupt. cleared by the user to disable the timer 0 interrupt. 0 ex0 set by the user to enable external interrupt 0 ( int0 ). cleared by the user to disable external interrupt 0 ( int0 ). ipinterrupt priority register sfr address: b8h power-on default: 00h bit addressable: yes table 59. ip sfr bit designations bit no. name description 7 ----- not implemented. write dont care. 6 padc adc interrupt priority (1 = high; 0 = low). 5 pt2 timer 2 interrupt priority (1 = high; 0 = low). 4 ps uart serial port interrupt priority (1 = high; 0 = low). 3 pt1 timer 1 interrupt priority (1 = high; 0 = low). 2 px1 int0 (external interrupt 1) priority (1 = high; 0 = low). 1 pt0 timer 0 interrupt priority (1 = high; 0 = low). 0 px0 int0 (external interrupt 0) priority (1 = high; 0 = low).
aduc845/aduc847/aduc848 rev. b | page 86 of 108 ieip2s e co nd a r y i n t e rr u p t e n a b l e r e g i st e r s f r a ddr ess: a9h po w e r - o n d e f a u l t : a 0 h bi t a d dress a bl e: n o t a bl e 60. ieip2 b i t desig n a t i o ns bit no . name description 7 ---- not i m plemen ted . w r ite d o n t c a r e . 6 pti t ime i n t e r v al c o un t e r i n t e rrupt p r iorit y se tting ( 1 = h i gh, 0 = l o w). 5 ppsm p o w e r supply m o nit o r i n t e rrupt p r iorit y se tting ( 1 = h i gh, 0 = l o w). 4 psi spi/i 2 c i n ter r upt p r ior i t y s e tting ( 1 = h i gh, 0 = l o w) . 3 ---- this bit must c o n t ain 0. 2 e t i set b y the user t o enable th e time in t e r v al c o un ter in t e rrupt. clear e d b y the u s er t o disable the time in t e r v al coun t e r in t e rrupt. 1 epsmi s e t b y the user t o enable the pow er sup p ly monit o r in t e rrupt. clear e d b y the user to disable the po w e r sup p ly monitor in ter r u p t. 0 esi set b y the user t o enable the spi/ i 2 c s e ri a l po r t i n t e rr up t. clear e d b y the user to disable the spi/i 2 c s e ri a l po r t i n t e rr up t. interrup t priori t y the i n t e r r u p t e n a b le r e g i s t ers a r e wr i t t e n b y t h e us er t o ena b le indivi d u a l i n t e r r u p t s o ur ces; t h e in t e r r u p t p r io r i ty r e g i st ers al lo w t h e us er to s e le c t on e o f tw o p r io r i ty le v e ls f o r e a c h i n t e rr u p t . a h i gh p r i o ri t y in t e rr u p t c a n in t e rr u p t th e se r v i c e r o u t ine o f a lo w p r io r i ty in t e r r u p t, an d if tw o in t e r r u p ts o f dif f er en t p r io r i t i es o c c u r a t t h e s a m e t i m e , t h e hig h er le ve l in t e r r u p t is s e r v ice d f i rst . an i n t e r r u p t ca n n o t b e in ter r u p t e d b y a n o t h e r i n ter r u p t o f t h e s a m e pr io r i ty le ve l. i f t w o in t e r r u p ts o f th e sa m e p r i o r i ty l e v e l occu r s i m u l t a n e o u s l y , the po llin g s e q u e n c e , as sh o w n in t a b l e 61, is obs e r v ed . t a b l e 61. p r i o rit y w i thin i n t e rr u p t l e v e l interrup t vec t ors w h en an i n ter r u p t o c c u rs, t h e p r og ra m co un t e r is p u sh e d o n t o t h e st ack, an d t h e co r r esp o ndi n g in ter r u p t ve c t o r addr ess is l o a d e d i n to t h e pro g r a m c o u n te r . th e i n te r r upt ve c t or a ddre s s e s a r e s h o w n i n t a b l e 62. t a bl e 62. i n t e rr up t v e c t o r a d dress e s sou r c e v e c t or a d d r e s s ie0 0003h tf0 000bh ie1 0013h tf1 001bh ri + ti 0023h tf2 + exf2 002bh rd y0/rd y 1 ( a d u c845 only) 0033h ispi/i2ci 003bh psmi 0043h tii 0053h wds 005bh s o ur c e p r iorit y description psmi 1 (h ighes t ) p o w e r suppl y m o nit o r i n t e rrupt wds 2 w a tchd og t imer i n ter r u p t ie0 2 ex ter n al i n ter r upt 0 rd y0/rd y 1 3 adc i n ter r upt tf0 4 t imer/c o u n ter 0 i n ter r upt ie1 5 ex ter n al i n ter r upt 1 tf1 6 t imer/c o u n ter 1 i n ter r upt ispi/i2ci 7 spi/i 2 c i n ter r u p t ri / t i 8 u a rt se ri a l p o r t i n t e rr up t tf2/exf2 9 t imer/c o u n ter 2 i n ter r upt tii 11 (l o w est) t imer i n t e r v al c o un t e r i n t e rrupt
aduc845/aduc847/aduc848 rev. b | page 87 of 108 hardw a re design conside r a t ions this s e c t io n o u t l in e s s o m e o f t h e k e y ha r d wa r e desig n co n s idera t io n s t h a t m u st b e ad d r ess e d w h en in teg r a t ing t h e aduc845/adu c 847/adu c 84 8 in t o an y ha r d wa r e sys t em. external memor y interf a c e i n a d d i t i o n t o th e i r i n t e rn a l p r o g r a m a n d d a ta m e m o ri e s , th e p a r t s ca n acces s u p t o 16 mb yt es o f ext e r n al da t a mem o r y ( s r a m ) . n o e x te r n a l pro g r a m me mor y a c c e ss i s a v ai l a bl e. t o b e g i n exe c u t in g co de, t i e t h e ea (ex t er na l access) p i n h i g h . whe n ea is hig h (p u l led u p t o v dd see f i gur e 7 0 ), user p r og ra m exe c u t io n s t a r ts a t a d dr es s 0 i n t h e i n t e r n al 62- k b yt e flash / ee co d e sp ace. w h e n exe c u t in g f r o m i n ter n a l co de sp ac e, acces s es t o t h e p r og ra m s p ace a b o v e f7ffh (62 k b yt es) a r e r e ad as n o p inst r u c t io n s . n o t e t h a t a seco n d v e r y i m po r t a n t fun c ti o n o f th e ea pi n i s des c r i b e d i n t h e sin g le -pin e m u l a t ion m o de s e c t io n u n der t h e o t h e r h a r d wa re c o n s i d era t io ns s e c t io n. f i g u re 6 2 s h o w s a h a rdw a re c o n f i g u r a t i o n f o r a c c e ss i n g up to 64 k b yt es o f exter n al da t a m e mo r y . this in ter f ace is s t anda r d t o a n y 8051-com p a t ib le m c u . latch sram oe a8?a15 a0?a7 d0?d7 (data) aduc845/ aduc847/ aduc848 rd p2 ale p0 we wr 04741-059 f i g u re 62. e x ter n a l d a t a m e m o r y int e r f ac e ( 64-k b y t e addr es s spa c e) i f acces s t o m o re tha n 64 k b yt es o f ram is desir e d , a f e a t ur e unique t o t h e micr o c on v e r t er al lo w s addres s i n g u p t o 1 6 m b ytes o f ext e r n a l r a m sim p ly b y ad din g an ot h e r la tch as sh o w n i n f i gur e 63. latch p2 ale p0 latch sram a8 ? a15 a0?a7 d0 ?d7 (data) a16?a23 oe rd we wr aduc845/ aduc847/ aduc848 04741-060 f i gure 63. e x ter n a l d a t a me m o r y inter f ac e ( 16-mbt y e addr ess spa c e) i n ei t h e r im p l em en ta ti o n , p o r t 0 (p 0) se r v e s a s a m u l t i p l e x e d addr es s / da t a b u s. i t emi t s t h e lo w b y te o f t h e da t a p o i n t e r (d p l ) as an a d dr e s s , w h i c h is la t c he d b y a l e p r io r t o d a t a b e i n g pl ac e d o n t h e b u s b y t h e p a r t s (wr i t e op era t ion) o r t h e ext e r n al da t a m e m o r y (r e a d o p era t ion). p o r t 2 (p2) p r o v ides t h e da t a p o in t e r p a ge b y te ( d pp ) to b e l a tc he d b y al e , fol l o w e d b y t h e da t a p o i n te r h i g h b y t e ( d ph ) . i f no l a tch i s c o n n e c te d to p 2 , dpp i s ig n o re d b y t h e s r am , and t h e 8 051 s t anda rd of 64-k b y t e ex t e r n al d a t a me mor y a c c e ss i s m a i n t a i n e d . the fol l o w in g e x a m ple sh o w s t h e co de us e d t o wr i t e da t a t o ext e r n al da t a mem o r y . mov dpp, 10h ;set addr to 100000h mov dph, 00h mov dpl, 00h mov a, b ;write char b? (42h) movx @dptr,a ;move to dpp:dph:dpl addr po wer supplies the p a r t s o p era t io nal p o w e r su p p l y v o l t a g e ra n g e is 2.7 v t o 5 . 2 5 v . a l th o u gh th e g u a r a n t e ed d a ta s h ee t s p ec i f i c a t i o n s a r e g i v e n o n l y f o r p o w e r s u p p lies wi thin 2.7 v t o 3.6 v a nd 4.75 v t o 5.25 v (5% o f th e n o minal 5 v lev e l ), t h e chi p f u n c tio n s eq ual l y w e l l a t an y p o w e r su p p ly lev e l betw een 2.7 v a nd 5.25 v . s e pa r a t e a n al og a n d di gi tal po w e r s u p p l y p i n s (a v dd a nd d v dd , re s p e c t i v e ly ) a l l o w a v dd t o b e kep t rel a t i ve l y f r e e o f t h e no isy di g i t a l si g n als o f t e n p r esen t o n a s y s t em d v dd l i ne . i n t h is mo de , th e pa r t ca n also o p e r a t e wi th s p li t s u p p l i e s, tha t is , u s in g di f f e r en t v o l t a g e s u p p ly l e vel s for e a ch sup p ly . f o r e x am pl e, t h e s y ste m ca n b e desig n e d to o p er a t e w i t h a d v dd vol t age l e vel of 3 v and th e a v dd lev e l c a n b e a t 5 v , o r vice vers a , if r e q u ir ed . a typ i c a l spl i t- su p p ly c o n f ig u r a t ion is s h ow n i n f i g u re 6 4 . digital supply analog supply dv dd agnd av dd dgnd ? + ? + 0.1 f 0.1 f 10 f 10 f aduc845/ aduc847/ aduc848 04741-061 6 5 4 22 36 51 50 38 37 23 f i gur e 6 4 . ex t e rnal du al -suppl y c o nne c ti ons (56-l e ad lfcs p pin numb er ing ) a s a n a l te r n a t iv e to pro v i d i n g t w o s e p a r a te p o we r suppl i e s , av dd ca n b e ke p t q u ie t b y placi n g a sma l l s e r i e s r e sist o r a n d / o r f e rri t e bead betw ee n i t a n d d v dd , a nd t h en de c o u p lin g a v dd s e p a ra te ly t o g r o u nd . an exam ple o f t h is co nf igura t io n is sho w n in f i gur e 65. i n this co nf igura t io n, o t h e r a n alog cir c ui tr y (s uc h
aduc845/aduc847/aduc848 rev. b | page 88 of 108 as o p a m ps an d vol t a g e r e fer e n c e) ca n b e p o w e re d f r o m t h e av dd su p p ly l i ne as wel l . dv dd agnd av dd dgnd digital suppl y ? + bead 1.6 ? 0.1 f 0.1 f 10 f 10 f aduc845/ aduc847/ aduc848 04741-062 6 5 4 22 36 51 50 38 37 23 f i g u re 65. e x ter n a l sing l e -sup p l y con n ec t i ons (56-l e ad lfcs p pin numb er ing ) n o tice tha t in b o th f i gur e 64 and f i gur e 65 a l a rg e val u e (10 f) r e s e r v o i r ca p a ci t o r si ts o n d v dd a n d a s e pa r a t e 1 0 f c a pa c i t o r si ts o n a v dd . al s o , lo cal de co u p lin g c a p a ci t o rs (0.1 f) a r e lo ca t e d a t each v dd p i n o f t h e chi p . a s p e r st anda r d desig n p r ac t i ce , b e s u re t o i n cl ude al l o f t h es e ca p a c i to rs a n d e n s u r e t h a t t h e smal ler ca p a ci t o rs a r e clos er t h a n t h e 10 f ca p a ci t o rs to e a ch v dd p i n wi th le ad len g ths as s h o r t as p o ssi b l e . c o nn e c t t h e g r o u nd t e r m inal o f e a ch o f t h es e c a p a ci t o rs dir e c t l y t o t h e un d e rly i n g g r o u nd plan e. f i na l l y , n o te t h a t , a t a l l t i m e s , t h e a n a l o g a nd d i g i t a l g r o u n d pin s o n t h e p a r t m u st b e r e fer e nce d to t h e s a m e sy stem g r o u nd r e fer e n c e p o in t. i t is r e co mm e nde d tha t t h e lfcs p p a ddle be s o lde r e d t o en s u r e me c h a n ic al st abi l ity b u t b e f l o a te d wit h re sp e c t to s y ste m v dd s or g r ou nd s . po wer- on reset oper a t ion an in t e r n a l p o w e r - o n r e s e t (por) is im ple m e n t e d o n t h e aduc845/adu c 847/adu c 84 8. 3 v p a r t fo r dv dd b e lo w 2.63 v , t h e in ter n al po r h o lds th e p a r t in r e s e t. as dv dd r i s e s a b o v e 2.63 v , an in t e r n al tim e r tim e s o u t f o r typ i c a l l y 128 m s bef o r e the p a r t is r e leas e d f r o m r e s e t. th e us er m u st e n su re t h a t t h e p o we r su pply has a t l e ast re ache d a st abl e 2.7 v minim u m lev e l b y this t i m e . l i k e wis e o n p o w e r - do wn, t h e in t e r n al por h o lds t h e p a r t in r e s e t un t i l t h e p o w e r s u p p l y d r op s b e l o w 1 v . f i g u re 6 6 i l lu st r a te s t h e op e r a t i o n of t h e in t e r n a l por . 128ms typ 1.0v typ 128ms typ 2.63v typ 1.0v typ internal core reset dv dd 04741-063 f i g u re 66. 3 v p a r t por oper at i o n 5 v p a r t fo r dv dd b e lo w 4.5 v , t h e in t e r n al po r h o lds th e p a r t in r e s e t. as dv dd r i s e s a b o v e 4.5 v , an in t e r n al t i m e r tim e s o u t f o r a p p r o x ima t e l y 128 m s bef o r e t h e p a r t is r e leas e d f r o m r e s e t. the u s e r m u st e n su re t h a t t h e p o we r su p p ly has re ache d a s t abl e 4.75 v min i m u m le vel b y t h is t i me. l i ke wis e on p o w e r - do w n , t h e in t e r n al por h o lds t h e p a r t in r e s e t un t i l t h e p o w e r s u p p l y dr o p s b e lo w 1 v . f i gur e 67 il l u s t ra t e s this o p era t io n. 128ms typ 1.0v typ 128ms typ 4.5v typ 1.0v typ internal core reset dv dd 04741-087 f i g u re 67. 5 v p a r t por o p er at i o n power c o n s umpti o n the d v dd p o w e r su p p ly c u r r en t co n s um p t io n is sp e c if ie d in n o r m a l and p o w e r - do w n m o d e s. t h e a v dd p o we r su p p ly c u r r en t is sp e c if ie d wi t h t h e a n a l og p e r i ph era l s dis a b l e d . t h e n o r m al m o de p o w e r co n s u m p t i o n r e p r es en t s t h e c u r r en t dr a w n fr o m d v dd b y t h e d i g i t a l c o re. t h e ot he r on - c h i p p e r i p h e r a l s (s uc h as t h e wa tc h d og t i m e r a n d p o w e r su p p l y m o ni t o r) co n s u m e n e g l ig i b le c u r r en t an d a r e t h er efo r e i n cl ude d w i t h t h e n o r m al o p er a t i n g c u r r en t. th e us er m u s t add an y c u r r en ts s o ur ce d b y t h e p a r a l l el a nd s e r i a l i/o p i n s , an d t h o s e s o ur ce d b y th e d a c t o d e t e rm i n e th e t o ta l cu rr e n t n eed ed a t th e a d u c 8 4 5/ aduc847/adu c 848 d v dd an d a v dd su p p ly p i ns . a l s o , c u r r e n t dr a w n f r o m t h e d v dd s u pp l y i n c r e a s e s b y approx i m a t el y 5 m a d u r i n g f l ash/e e eras e a nd p r og ra m c y cles. po wer-sa ving modes s e t t in g t h e p o wer - do w n m o de b i t, pc on.1, in t h e pc o n s f r des c r i be d in t a b l e 6, al lo ws t h e c h i p t o be s w i t ch e d f r o m n o r m a l m o de i n to f u l l p o w e r - do wn m o de. i n po w e r - d o w n m o d e , b o th th e p l l a n d th e c l oc k t o th e c o r e are stopp e d. t h e on - c h i p o s c i l l a tor c a n b e h a lt e d or c a n co n t i n ue t o os ci l l a t e , de p e n d in g o n t h e s t a t e o f t h e os ci l l a t o r p o w e r - do wn b i t (osc_p d) in t h e pll c o n s f r . th e ti c, dr i v en dir e c t ly f r o m t h e o s ci l l a to r , ca n a l s o b e e n a b le d d u r i ng p o we r - d o w n . h o we ve r , a l l ot he r on - c h i p p e r i p h e r a l s are s h ut do wn. p o r t p i n s r e ta in t h e i r log i c le v e l s in this m o de , b u t t h e d a c o u t p u t g o es t o a hig h im p e dan c e s t a t e (t hr e e -s t a t e ) w h ile ale a nd ps en o u t p uts a r e he ld lo w . ther e a r e f i v e w a ys t o ter m in a t e p o w e r - do wn mo de: ? as s e r t i n g t h e r e set pi n re t u r n s t o n o r m al m o de. al l reg i s t ers a r e s e t to t h eir r e s e t defa u l t va l u e and p r o g r a m exe c u t io n st a r ts a t t h e r e s e t ve c t or onc e t h e r e se t pi n i s d e - a ss e r te d.
aduc845/aduc847/aduc848 rev. b | page 89 of 108 ? cycling power all registers are set to their default state and program exe- cution starts at the reset vector approximately 128 ms later. ? time interval counter (tic) interrupt if the osc_pd bit in the pllcon sfr is clear, the 32 khz oscillator remains powered up even in power-down mode. if the time interval counter (wake-up/rtc timer) is enabled, a tic interrupt wakes the part from power-down mode. the cpu services the tic interrupt. the reti at the end of the tic isr returns the core to the next instruction after that one the enabled power-down. ? spi interrupt if the seripd bit in the pcon sfr is set, an spi interrupt, if enabled, wakes up the part from power-down mode. the cpu services the spi interrupt. the reti at the end of the isr returns the core to the next instruction after the one that enabled power-down. ? int0 interrupt if the int0pd bit in the pcon sfr is set, an external interrupt 0, if enabled, wakes up the part from power- down. the cpu services the interrupt. the reti at the end of the isr returns the core to the next instruction after the one that enabled power-down. wake-up from power-down latency even with the 32 khz crystal enabled during power-down, the pll takes some time to lock after a wake-up from power-down. typically, the pll takes about 1 ms to lock. during this time, code executes, but not at the specified frequency. some opera- tions, for example, uart communications, require an accurate clock to achieve the specified 50 hz/60 hz rejection from the adcs. therefore, it is advisable to wait until the pll has locked before proceeding with normal code execution. the following code can be used to wait for the pll to lock: waitforlock: mov a, pllcon jnb acc.6, waitforlock if the crystal is powered down during power-down, an additional delay is associated with the startup of the crystal oscillator before the pll can lock. typically taking about 150 ms, 32 khz crystals are inherently slow to oscillate. during this time before lock, code executes, but the exact frequency of the clock cannot be guaranteed. for any timing-sensitive operations, it is recommended to wait for lock by using the lock bit in pllcon as previously shown. an alternative way of saving power in power-down mode is to slow down the core clock by using the cd bits in the pllcon register. grounding and board layout recommendations as with all high resolution data converters, special attention must be paid to grounding and pc board layout of aduc845/ aduc847/aduc848-based designs in order to achieve optimum performance from the adcs and dac. although the parts have separate pins for analog and digital ground (agnd and dgnd), the user must not tie these to separate ground planes unless the two ground planes are connected together very close to the part as shown in the simplified example in figure 68a. in systems where digital and analog ground planes are connected together somewhere else (at the systems power supply, for example), they cannot be connected again near the part since a ground loop would result. in these cases, tie the agnd and dgnd pins of the part to the analog ground plane, as shown in figure 68b. in systems with only one ground plane, ensure that the digital and analog components are physically separated onto separate halves of the board such that digital return currents do not flow near analog circuitry and vice versa. the parts can then be placed between the digital and analog sections, as shown in figure 68c. in all of these scenarios, and in more complicated real-life applications, keep in mind the flow of current from the supplies and back to ground. make sure that the return paths for all currents are as close as possible to the paths the currents took to reach their destinations. for example, do not power components on the analog side of figure 68b with dv dd since that would force return currents from dv dd to flow through agnd. also, try to avoid digital currents flowing under analog circuitry, which could happen if the user placed a noisy digital chip on the left half of the board in figure 68c. whenever possible, avoid large discontinuities in the ground plane(s) (such as are formed by a long trace on the same layer), since they force return signals to travel a longer path. make all connections directly to the ground plane, with little or no trace separating the pin from its via to ground.
aduc845/aduc847/aduc848 rev. b | page 90 of 108 dgnd agnd p l ace analog c omponents h ere p l ace digital c omponents h ere gnd p l ace analog c omponents h ere p l ace digital c omponents h ere dgnd a. agnd p l ace analog c omponents h ere p l ace digital c omponents h ere b. c. 04741-064 f i gure 6 8 . s y st em gr o u ndi n g s c h e m e s i f th e use r p l a n s t o co nn ec t fas t logi c si g n als (r i s e/ fall tim e < 5 n s ) t o a n y o f the aduc845/ad uc847/aduc848 s dig i tal in p u ts, add a s e r i es r e sis t o r t o eac h r e l e va n t l i n e t o k eep r i s e a nd fal l tim e s lo n g er than 5 n s a t t h e p a r t s in p u t p i n s . a val u e o f 100 ? o r 200 ? is us ual l y s u f f i cien t t o p r ev en t hig h s p eed sig n als f r o m c o u p l i n g ca pa c i ti v e l y in t o th e p a r t a n d a f f e cti n g th e a c cu ra c y o f ad c con v ersion s. w h en usi n g t h e lfcs p p a cka g e, i t is r e co mm e nde d t h a t t h e p a ddle u n der n e a t h t h e chi p b e s o lder e d t o t h e b o a r d t o p r o v ide max i m u m m e cha n ica l st ab i l i t y . h o w e ver , i t is re co mme n d e d tha t t h is p a ddle n o t be g r o u n d e d b u t lef t f l o a ting. al l r e s u l t s a nd sp e c if ica t ion s co n t ai n e d in t h is da t a sh e e t ar e t a k e n o r re c o rd e d w i t h t h e p a d d l e f l o a t i ng . s y st em s e lf- i dentific ation i n s o me ha r d war e desig n s, i t ma y be adva n t a g eous f o r th e s o f t wa r e t o be ab le t o iden tif y t h e h o s t m i cr oc o n v e r t er . the chi p id s f r is a r e ad-o nl y r e g i s t er lo ca t e d a t s f r addr es s c 2 h. th e u p p e r ni b b l e o f t h is s f r de si g n a t es t h e m i cr oc o n v e r t e r wi t h i n t h e - ? ad c fa mi l y . u s er s o f t wa r e c a n r e ad t h is s f r t o iden t i f y t h e h o st micr oc o n v e r t er a n d t h er efo r e exe c u t e s l i g h t l y dif f er en t co de if r e q u ir ed . the chip id s f r r e ads as f o l l o w s f o r t h e - ? ad c fami l y o f micr oc o n v e r t er p r o d u c ts. n o t e t h a t t h e aduc845/adu c 847/adu c 84 8 a r e tr ea t e d as o n e p a r t as fa r as th e chip i d is c o n c er n e d. t a bl e 63. chipid v a l u es f o r - ? mi cr oc o n v e r t e r p r o d u c ts p a r t chipid aduc816 1xh aduc824 0xh aduc836 3xh aduc834 2xh aduc845/aduc 847/aduc848 axh clock oscillat o r a s des c r i be d earlier , t h e co r e c l o c k f r eq uen c y f o r th e ad uc84 5/ aduc847/adu c 848 is g e n e ra ted f r o m a n o n -chi p p ll tha t lo c k s o n t o a m u l t i p le (384 tim e s ) o f 32.768 kh z. the l a t t e r is ge ne r a te d f r om an i n te r n a l cl o c k o s c i l l a t or . t o u s e t h e i n te r n a l c l o c k os cil l a t o r , co nn ec t a 32.76 8 kh z p a ral l e l res o na n t cr ys tal bet w een xt al1 a n d xt a l 2 a s s h o w n in f i gur e 69. xtal2 32.768khz 12pf 12pf xtal1 to internal pll aduc845/aduc847/aduc848 04741-065 32 33 f i g u re 69. cr y s t a l conne c t iv it y t o a d u c 84 5/a d uc 84 7/a d uc84 8 a s sho w n in t h e typ i ca l ext e r n al cr ys tal co nn e c t i o n dia g ra m in f i gur e 69, tw o in t e r n al 12 pf c a p a ci t o rs a r e p r o v ided on-c hi p . th es e a r e co nn e c t e d in ter n ally , di r e ctl y t o t h e xt al1 a n d xt al2 pi ns . t h e tot a l i n put c a p a c i t a nc e a t b o t h pi ns i s d e t a i l e d i n t h e s p e c if ica t io n s t a b l e . n o t e t h a t t h e t o t a l c a p a ci t a n c e r e q u ir e d fo r a p a r t i c u l ar c r y s t a l m u s t be in acco rdance wi t h t h e cr y s t a l man u fac t urer . h o we ver , i n m o st cas e s, no addi t i onal ex t e r n al ca p a ci tan c e is re qu i r e d a b o v e t h a t a l re a d y supp l i e d on - c h i p . o t her har d w a re c o nsider a t ions in- c irc u it s e rial d o wnloa d a c c e ss n e a r l y al l adu c 845/adu c 84 7/aduc848 desig n s can take ad van t a g e o f t h e in-cir c u i t r e p r og ra mma b i li ty o f t h e chi p . this is acco m p lish e d b y a co nn ec t i o n t o t h e p a r t s u a r t , whic h r e q u ir es a n ext e r n al rs-232 c h i p f o r lev e l tra n s l a t io n if do wn - lo adin g co de f r o m a pc. b a sic co nf igura t io n of a n rs-232 co nn ec t i o n is sh o w n in f i gur e 70 wi th a sim p l e ad m3202- bas e d c i r c ui t. i f us ers w o u l d ra t h er n o t in c l u d e a n rs-232 chi p o n t h e ta rg et bo a r d , r e f e r t o a p p l ica t ion n o t e u c 006, a 4 - w i r e u a r t - t o - p c i n t e r f a c e a v a i l a b l e a t ww w . a n a l o g . c o m / m i c r o c o n v e r t e r , fo r a sim p le (a n d zer o -cost - p e r - bo a r d) met h o d o f ga inin g in-cir c u i t s e r i al do wnlo ad ac cess to t h e p a r t .
aduc845/aduc847/aduc848 rev. b | page 91 of 108 c1+ v+ c1 ? c2+ c2 ? v? t2out r2in v cc gnd t1out r1in r1out t1in t2in r2out adm3202 rs-232 interface 1 1 2 3 4 5 6 7 8 9 dv dd standard d-type serial comms connector to pc host notes 1. external uart transceiver integrated in system or as part of an external dongle as described in application note uc006. 0.1 f 0.1 f 0.1 f 0.1 f reset active high. (normally open) 35 34 43 44 1k ? dv dd 1k ? 2-pin header for emulation access (normally open) download/debug enable jumper (normally open) 32.768khz dv dd dv dd av dd av dd agnd agnd refin? refin+ p1.0/ain1 p1.1/ain2 p1.6/i exc 1/ain7 200 a/400 a excitation current rtd r ref 5.6k ? psen ea xtal2 xtal1 r eset rx d txd dv dd dgnd aduc845/aduc847/aduc848 lfcsp package 04741-088 11 4 5 6 7 8 56 1 17 18 19 22 36 51 37 38 50 23 0.1 f f i g u re 70. u a rt co nnec t iv i t y in t y pic a l sy s t em i n addi tion t o t h e basic u a r t co nn e c t i o n s, us ers als o n e e d a wa y t o tr igg e r t h e chi p in t o d o w n load m o de . thi s is a c co m p l i s h ed vi a a 1 k? p u l l - d o w n r e sist o r t h a t ca n b e j u m p er e d o n t o t h e ps e n p i n, a s s h o w n in f i g u r e 70 . t o g e t th e pa r t s i n t o d o w n loa d m o de, conne c t t h is j u m p er a nd p o w e r - c y cle t h e de vi ce (o r ma n u al l y r e s e t t h e de vic e , if a ma n u al r e s e t b u t t o n is a v ai lab l e), a nd i t is r e ad y t o r e cei v e a ne w p r og ra m s e r i al l y . w i t h t h e j u m p er r e m o ve d , t h e de vic e p o w e rs o n i n n o rm al m o d e (a n d r u n s th e p r ogra m ) w h en ev er po w e r i s c y c l e d or r e set i s to g g l e d. n o te t h a t ps en is n o r m al l y a n ou t p u t an d tha t i t is s a m p led as a n in p u t o n l y o n th e f a l l ing edg e o f res e t , tha t is, a t p o w e r - o n o r u p o n an ext e r n al ma n u a l r e s e t. n o t e als o t h a t if an y ext e r n a l cir c ui t r y un in t e n t io n a l l y p u l l s ps en lo w d u ri n g po w e r - o n o r r e se t ev en ts , i t co ul d ca us e th e ch i p t o en t e r do wn lo ad m o d e a nd fa i l to b e g i n us er co d e exe c u t io n. t o p r e v en t t h is, ens u r e t h a t n o exter n al sig n als a r e ca p a b l e o f pu l l i n g t h e ps en p i n lo w , except fo r t h e ext e r n al ps en ju mp e r i t s e lf o r t h e m e t h o d o f do wnlo ad en t r y in us e d u r i n g a r e s e t o r p o w e r - c y cle co ndi t i on. em bedd e d s e r i al p o r t d e bu g g er f r o m a h a r d w a r e pe r s pecti v e , en tr y t o se ri al po r t d e b u g m o de i s i d e n ti cal t o t h e se ri al d o w n l o ad e n tr y seq u e n c e d e sc ri be d p r e v io us l y . i n fac t , bot h s e r i al do w n lo ad an d s e r i al p o r t de b u g m o des a r e es s e n t ial l y on e m o de o f o p era t io n us e d in tw o dif f er en t w a ys.
aduc845/aduc847/aduc848 rev. b | page 92 of 108 the serial port debugger is fully contained on the device, unlike rom monitor type debuggers, and, therefore, no external memory is needed to enable in-system debug sessions. single-pin emulation mode built into the aduc845/aduc847/aduc848 is a dedicated controller for single-pin in-circuit emulation (ice). in this mode, emulation access is gained by connection to a single pin, the ea pin. normally on the 8051 standard, this pin is hardwired either high or low to select execution from internal or external program memory space. note that external program memory or execu- tion from external program memory is not allowed on the devices. to enable single-pin emulation mode, users need to pull the ea pin high through a 1 k? resistor as shown in figure 70. the emulator then connects to the 2-pin header also shown in figure 70. to be compatible with the standard connec- tor that comes with the single-pin emulator available from accutron limited (www.accutron.com), use a 2-pin 0.1-inch pitch friction lock header from molex (www.molex.com) such as part number 22-27-2021. be sure to observe the polarity of this header. as shown in figure 70, when the friction lock tab is at the right, the ground pin should be the lower of the two pins when viewed from the top. typical system configuration a typical aduc845/aduc847/aduc848 configuration is shown in figure 70. figure 70 also includes connections for a typical analog measurement application of the parts, namely an interface to a resistive temperature device (rtd). the arrangement shown is commonly referred to as a 4-wire rtd configuration. here, the on-chip excitation current sources are enabled to excite the sensor. the excitation current flows directly through the rtd generating a voltage across the rtd proportional to its resistance. this differential voltage is routed directly to one set of the positive and negative inputs of the adc (ain1, ain2, respectively in this case). the same current that excited the rtd also flows through a series resistance, r ref , generating a ratiometric voltage reference, v ref . the ratiometric voltage reference ensures that variations in the excitation current do not affect the measurement system since the input voltage from the rtd and reference voltage across r ref vary ratiometrically with the excitation current. resistor r ref must, however, have a low temperature coefficient to avoid errors in the reference voltage overtemperature. r ref must also be large enough to generate at least a 1 v voltage reference. the preceding example shows just a single differential adc connection using a single reference input pair. the aduc845/ aduc847/aduc848 have the capability of connecting to five differential inputs directly or ten single-ended inputs (lfcsp package only) as well as having a second reference input. this arrangement means that different sensors with different reference ranges can be connected to the part with the need for external multiplexing circuitry. this arrangement is shown in figure 71. the bridge sensor shown can be a load cell or a pressure sensor. the rtd is shown using a reference voltage derived from the r ref resistor via the refin inputs, and the bridge sensor is shown using a divided down av dd reference via the refin2 inputs.
aduc845/aduc847/aduc848 rev. b | page 93 of 108 dv dd 0.1 f reset active high. (normally open) 35 34 43 44 1k ? dv dd 1k ? 2-pin header for emulation access (normally open) download/debug enable jumper (normally open) rs232 connection dv dd dv dd av dd av dd av dd agnd agnd refin? refin+ p1.0/ain1 p1.1/ain2 200 a/400 a excitation current rtd r r psen ea dgnd dv dd xtal2 xtal1 r eset rx d txd dv dd dgnd 04741-067 11 4 5 6 7 8 56 1 p1.2/ain3/refin2+ ain9 ain10 p1.3/ain4/refin2? r ref 5.6k ? 2 15 16 3 17 18 19 22 36 51 37 38 50 23 0.1 f p1.6/i exc 1/ain7 aduc845/aduc847/aduc848 lfcsp package f i gure 71. d u al r e fer e nc e t y p i c a l con n ec tiv i t y
aduc845/aduc847/aduc848 rev. b | page 94 of 108 quickstart development system the quickstart development system is an entry-level, low cost development tool suite supporting the aduc8xx microconverter product family. the system consists of the following pc-based (windows?-compatible) hardware and software development tools: hardware: evaluation board and serial port programming cable. software: serial download software. miscellaneous: cd-rom documentation and prototype evaluation board. a brief description of some of the software tools and components in the quickstart system follows. downloadin-circuit serial downloader the serial downloader is a windows application that allows the user to serially download an assembled program (intel? hexa- decimal format file) to the on-chip program flash memory via the serial com port on a standard pc. application note uc004 details this serial download protocol and is available from www.analog.com/microconverter . aspireide the aspire? integrated development environment is a windows application that allows the user to compile, edit, and debug code in the same environment. the aspire software allows users to debug code execution on silicon using the microconverter uart serial port. the debugger provides access to all on-chip peripherals during a typical debug session as well as single-step, animate (automatic single stepping), and break-point code execution control. note that the aspire ide is also included as part of the quickstart-plus system. as part of the quickstart-plus system the aspire ide also supports mixed level and c source debugging. this is not available in the quickstart system where the program is limited to assembly only. quickstart-plus development system the quickstart-plus development system offers users enhanced nonintrusive debug and emulation tools. the system consists of the following pc-based (windows-compatible) hardware and software development tools: hardware: prototype board, accutron nonintrusive single-pin emulator. software: aspire integrated development environment. features full c and assembly emulation using the accutron single-pin emulator. miscellaneous: cd-rom documentation.
aduc845/aduc847/aduc848 rev. b | page 95 of 108 timing specifica t ions a c in pu ts d u r i n g t e st in g a r e d r i v en a t d v dd C 0.5 v f o r l o g i c 1 a nd 0.45 v f o r l o g i c 0. t i ming m e as ur em en ts a r e made a t v ih mi n fo r l o g i c 1 a nd v il m a x f o r l o g i c 0 a s sh ow n i n fi g u re 7 2 . f o r timin g p u r p os es, a p o r t p i n is n o lo n g er f l o a tin g w h en a 100 mv c h a n g e f r o m lo ad v o l t a g e o c c u rs. a p o r t p i n beg i n s t o f l o a t wh e n a 100 mv c h a n g e f r o m th e lo ade d v oh /v ol le ve l o c c u rs as sh o w n in f i gur e 72. c lo a d f o r al l o u t p u t s = 80 pf , unles s o t h e r w is e no t e d . av dd = 2.7 v t o 3.6 v o r 4.75 v t o 5.25 v , d v dd = 2.7 v t o 3.6 v o r 4.75 v t o 5.25 v ; al l sp ecif ica t io ns t min to t max , unles s o t her w is e note d. t a bl e 64. c l o c k inpu t (e x t e r na l c l o c k d r iv en xt al1) p a r a met e r 32.768 kh z ex ternal c r y s t a l mi n ty p ma x unit t ck x t al1 p e r i od 30.52 s t ck l x t al1 w i dth l o w 6.26 s t ck h x t al1 w i dth h i gh 6.26 s t ck r x t al1 r i se t ime 9 ns t ck f x t al1 f a ll t ime 9 ns 1/t co r e c o r e c l ock f r e q uenc y 1 0.098 1.57 12.58 mh z t co r e c o r e c l ock p e r i o d 2 0.636 s t cy c m a chine c y cle time 3 10.2 0.636 0.08 s 1 aduc845/ aduc84 7/aduc848 in t e r n al pll locks o n t o a multiple (512 times) of the 32.768 k hz ex t e r n al cr y s tal fr eq uenc y t o pr ovide a st a b le 12.58 mh z i n t e rn a l cl ock f o r t h e sy st em . t h e c o r e ca n oper a t e a t t h i s fr eq uen c y or a t a bi n a r y subm ult i ple ca lle d c o r e _c l k , se le c t ed vi a t h e pl l c on sfr . 2 t h i s n u m b er i s m e a s ur e d a t t h e d e fa u l t c o r e _ c l k op er a t in g fr eq uen c y o f 1.5 7 mhz. 3 aduc845/ aduc84 7/aduc848 machine c y c l e time i s nomi nally defined as 1/ c o r e _clk . dv dd ? 0.5v 0.45v 0.2dv dd + 0.9v test points 0.2dv dd ? 0.1v v load ? 0.1v v load v load + 0.1v timing reference points v load ? 0.1v v load v load ? 0.1v 04741-077 f i g u re 72. ti m i ng w a vef o r m ch ar ac t e ris t i c s
aduc845/aduc847/aduc848 rev. b | page 96 of 108 t a bl e 65. e x te rn al d a t a memo r y re ad cy cle p a r a meter 12.58 m hz c o re clock 6.29 mh z c o re clock mi n ma x mi n ma x unit t rlrh rd p u lse w i dth 60 125 ns t av l l a ddr ess v a lid a f t e r ale l o w 60 120 ns t lla x a ddr ess hold a f t e r ale l o w 145 290 ns t rldv rd l o w to v a lid da ta i n 48 100 ns t rh d x da ta and a ddr es s hol d a f t e r rd 0 0 ns t rh dz da ta f l oa t a f t e r rd 150 625 ns t lldv ale l o w t o v a li d da ta i n 170 350 ns t av d v a ddr ess to v a lid da ta i n 230 470 ns t ll w l ale l o w t o rd or wr low 130 255 ns t av w l a d d r ess v a lid to rd or wr low 190 375 ns t rlaz rd l o w to a d d r ess f l o a t 15 35 ns t whl h rd or wr h i gh t o al e h i gh 60 120 ns 04741-078 a l e (o ) port 0 (i/o) port 2 (o) t whl h t lld v t llwl t rl rh t av w l t ll a x t av l l t rla z t rhdx t rhdz t av d v a0 [ a 7 (out) d a t a (in) a1 6 [ a2 3 a 8 a 1 5 t rldv psen (o) rd (o) f i gur e 7 3 . ex t e rnal da t a memo r y re ad c y c l e
aduc845/aduc847/aduc848 rev. b | page 97 of 108 t a bl e 66. e x te rn al d a t a memo r y wr ite cy c l e p a r a m e t e r 12.58 m hz c o re clock 6.29 mh z c o re clock mi n ma x mi n ma x unit t wl w h wr p u lse w i dth 65 130 ns t av l l a ddr ess v a lid a f t e r ale l o w 60 120 ns t lla x a ddr ess hold a f t e r ale l o w 65 135 ns t ll w l ale l o w t o rd or wr low 130 260 ns t av w l a d d r ess v a lid to rd or wr low 190 375 ns t qv w x da ta v a lid to wr tr a n s i t i o n 60 120 ns t qv w h da ta setup bef o r e wr 120 250 ns t whq x da ta and a ddr es s hol d a f t e r wr 380 755 ns t whl h rd or wr h i gh t o al e h i gh 60 125 ns 04741-079 a l e (o ) port 2 (o) t whl h t wl wh t ll w l t av w l t ll a x t av l l t qvwx t qvwh t whqx a0 [ a 7 da ta a1 6 [ a2 3 v 8 a 1 5 psen (o) wr (o) f i gure 74. e x ter n a l d a t a me m o r y write c y cl e t a bl e 67. i 2 c-c o mp a t ible i n terf a c e ti min g p a r a meter p a r a me t e r m i n ma x unit t l scl c k l o w p u lse w i dth 1.3 s t h scl c k h i gh p u lse w i dth 0.6 s t shd star t c o ndition hold t ime 0.6 s t dsu da ta s e tup t ime 100 s t dhd da ta hold t ime 0.9 s t rsu s e tup t ime f o r repea t ed star t 0.6 s t psu stop c o ndition s e tup t ime 0.6 s t bu f bus f r ee t ime b e t w ee n a stop c o ndition and a star t c o ndition 1.3 s t r r i se t ime of both scl c k and sd a t a 300 ns t f f a ll t ime of bot h scl c k and sd a t a 300 ns t su p 1 p u lse w i dth of spike sup p ress e d 50 ns __ __ __ __ __ __ __ __ __ __ __ __ __ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 1 i n put f i l t e r ing o n bo th the s c l o ck a n d s d a t a inputs sup p re ss es no ise s p ike s l e s s than 50 ns.
aduc845/aduc847/aduc848 rev. b | page 98 of 108 msb t bu f sd a t a (i/o) sclk (i) st op condition st ar t condition repea ted st ar t lsb a c k msb 1 2-7 8 9 1 s(r) ps t psu t dsu t shd t dhd t sup t dsu t dhd t h t sup t l t rsu t r t r t f t f 04741-080 f i g u re 75. i 2 c- com p at ibl e int e r f ac e ti ming
aduc845/aduc847/aduc848 rev. b | page 99 of 108 t a bl e 68. s p i ma s t er m o d e ti min g (cph a = 1) p a r a meter m i n t y p ma x unit t sl scl o ck l o w p u lse w i d t h 1 635 ns t sh scl o ck h i gh p u lse w i d t h 1 635 ns t da v da ta o utput v a l i d a f t e r scl o ck e d ge 50 ns t dsu da ta i n put s e tup t ime bef o r e s c l o ck e d ge 100 ns t dhd da ta i n put hold t ime a f ter scl o ck e d ge 100 ns t df da ta o utput f a ll t ime 10 25 ns t dr da ta o utput r i s e t ime 10 25 ns t sr scl o ck r i se t ime 10 25 ns t sf scl o ck f a ll t ime 10 25 ns __ __ __ __ __ __ __ __ __ __ __ __ __ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 1 c h arac t e r i zed un der the f o ll owing c o nd itions : a . c o r e c l oc k di vi de r bi t s cd 2, cd 1, a n d cd 0 i n pll c on s f r set t o 0, 1, a n d 1, r e spec t i v e ly , t h a t i s , c o r e c l ock f r eq uen c y = 1. 57 mhz. b . sp i bi t - r a t e sel e c t i o n bi t s spr 1 a n d s p r 0 i n sp ic on sfr set t o 0 a n d 0, r e sp ec t i v e ly . sclock ( cpol = 0) t dsu sclock ( cpol = 1) mosi miso msb lsb lsb in bits 6?1 bits 6 ? 1 t dhd t dr t dav t df t sh t sl t sr t sf msb in 04741-081 f i g u re 76. spi m a s t er m o de ti mi ng (c h p a = 1)
aduc845/aduc847/aduc848 rev. b | page 100 of 108 t a bl e 69. s p i ma s t er m o d e ti min g (cph a = 0) p a r a meter m i n t y p ma x unit t sl scl o ck l o w p u lse w i d t h 1 635 ns t sh scl o ck h i gh p u lse w i d t h 1 635 ns t da v da ta o utput v a l i d a f t e r scl o ck e d ge 50 ns t dosu da ta o utput s e tup bef o r e scl o ck e d ge 150 ns t dsu da ta i n put s e tup t ime bef o r e s c l o ck e d ge 100 ns t dhd da ta i n put hold t ime a f ter scl o ck e d ge 100 ns t df da ta o utput f a ll t ime 10 25 ns t dr da ta o utput r i s e t ime 10 25 ns t sr scl o ck r i se t ime 10 25 ns t sf scl o ck f a ll t ime 10 25 ns 1 c h arac t e r i zed un der the f o ll owing c o nd itions : a . c o r e c l oc k di vi de r bi t s cd 2, cd 1, a n d cd 0 i n pll c on s f r set t o 0, 1, a n d 1, r e spec t i v e ly , t h a t i s , c o r e c l ock f r eq uen c y = 1. 57 mhz. b . sp i bi t - r a t e sel e c t i o n bi t s spr 1 a n d s p r 0 i n sp ic on sfr set t o 0 a n d 0, r e sp ec t i v e ly . sclock ( cpol = 0) t dsu sclock ( cpol = 1) mosi miso msb lsb lsb in bits 6?1 bits 6?1 t dhd t dr t dav t df t dosu t sh t sl t sr t sf msb in 04741-082 f i g u re 77. spi m a s t er m o de ti mi ng (c h p a = 0)
aduc845/aduc847/aduc848 rev. b | page 101 of 108 t a bl e 70. s p i sl a v e m o d e timin g (cph a = 1) p a r a m e ter m i n t y p ma x unit t ss ss t o scl o ck e d ge 0 ns t sl scl o ck l o w p u lse w i dth 330 ns t sh scl o ck h i gh p u lse w i dth 330 ns t da v da ta o utput v a l i d a f t e r scl o ck e d ge 50 ns t dsu da ta i n put s e tup t ime bef o r e s c l o ck e d ge 100 ns t dhd da ta i n put hold t ime a f ter scl o ck e d ge 100 ns t df da ta o utput f a ll t ime 10 25 ns t dr da ta o utput r i s e t ime 10 25 ns t sr scl o ck r i se t ime 10 25 ns t sf scl o ck f a ll t ime 10 25 ns t sf s ss h i gh a f t e r scl o ck e d ge 0 ns miso mosi sclock ( cpol = 1) sclock ( cpol = 0) ss msb bits 6?1 lsb bits 6?1 lsb in t dhd t dsu t dr t df t dav t sh t sl t sr t sf t sfs msb in t ss 04741-083 f i g u re 78. spi sl ave m o de ti m i ng (ch p a = 1)
aduc845/aduc847/aduc848 rev. b | page 102 of 108 t a bl e 71. s p i sl a v e m o d e timin g (cph a = 0) p a r a m e ter m i n t y p ma x unit t ss ss t o scl o ck e d ge 0 ns t sl scl o ck l o w p u lse w i dth 330 ns t sh scl o ck h i gh p u lse w i dth 330 ns t da v da ta o utput v a l i d a f t e r scl o ck e d ge 50 ns t dsu da ta i n put s e tup t ime bef o r e s c l o ck e d ge 100 ns t dhd da ta i n put hold t ime a f ter scl o ck e d ge 100 ns t df da ta o utput f a ll t ime 10 25 ns t dr da ta o utput r i s e t ime 10 25 ns t sr scl o ck r i se t ime 10 25 ns t sf scl o ck f a ll t ime 10 25 ns t doss da ta o utput v a l i d a f t e r ss ed g e 20 ns t sf s ss h i gh a f t e r scl o ck e d ge ns miso mosi sclock ( cpol = 1) sclock ( cpol = 0) ss msb bits 6? 1 lsb bits 6?1 lsb in t dhd t dsu t dr t df t dav t doss t sh t sl t sr t sf t sfs msb in t ss 04741-084 f i g u re 79. spi sl ave m o de ti m i ng (ch p a = 0)
aduc845/aduc847/aduc848 rev. b | page 103 of 108 t a bl e 72. u a r t ti min g (s hift registe r mo d e ) p a r a meter 12.58 m hz c o re_clk v a riable c o re_ clk m i n t y p ma x m i n t y p ma x unit t x lxl s e r i al p o r t clock c y cle t ime 954 12t co re ns t q vxh o utput da ta s e tup to clock 662 ns tdvxh i n put da ta s e tup to clock 292 ns t x hd x i n put da ta hold a f t e r clock 0 ns t x hq x o utput da ta ho ld a f t e r clock 22 ns set ri or set ti bit 6 t xlxl txd (output clock) rxd (output data) rxd (input data) bit 1 lsb lsb bit 1 bit 6 msb t xhqx t qvxh t dvxh t xhdx 04741-086 f i gure 80. u a rt t i ming in shif t register m o de
aduc845/aduc847/aduc848 rev. b | page 104 of 108 outline dimensions compliant to jedec standards mo-112-ac-1 sea t i n g p l ane view a 2.45 max 1.03 0.88 0.73 t o p v i ew (p i n s d o w n ) 1 39 40 13 14 27 26 52 pin 1 14.15 13.90 sq 13.65 7.80 ref 10.20 10.00 sq 9.80 0.38 0.22 0. 25 min 2.10 2.00 1.95 7 0 0.10 coplanarity view a rotated 90 ccw 10 6 2 0.23 0.11 0.65 bsc lead pitch lead width f i g u re 81. 5 2 -l ead m e t r ic q u ad f l at p a ckag e [m qfp ] (s-52- 2) di me nsio ns sho w n i n mi ll im e t e r s pin 1 indicator top view 7.75 bsc sq 8.00 bsc sq 1 56 14 15 43 42 28 29 6.25 6.10 sq 5.95 0.50 0.40 0.30 0.30 0.23 0.18 0.50 bsc 0.20 ref 12 max 0.80 max 0.65 typ 1.00 0.85 0.80 6.50 ref seating plane 0.60 max 0.60 max pin 1 indicator coplanarity 0.08 0.05 max 0.02 nom 0.25 min exposed pad (bottom view) compliant to jedec standards mo-220-vlld-2 f i gure 82. 5 6 -l ead l e ad f r a m e ch ip s c a l e p a ck ag e [lfcs p ] 8 mm 8 m m b o d y , v e r y thin q u ad (c p - 5 6 ) di me nsio ns sho w n i n mi ll im e t e r s
aduc845/aduc847/aduc848 rev. b | page 105 of 108 ordering guide model t p 1 p t temperature range package description package option aduc845bs62-5 ?40c to +125c 52-lead plasti c quad flatpack, 62-kbyte, 5 v s-52-2 aduc845bs62-3 ?40c to +125c 52-lead plasti c quad flatpack, 62-kbyte, 3 v s-52-2 aduc845bs8-5 ?40c to +125c 52-lead plasti c quad flatpack, 8-kbyte, 5 v s-52-2 aduc845bs8-3 ?40c to +125c 52-lead plasti c quad flatpack, 8-kbyte, 3 v s-52-2 aduc845bcp62-5 ?40c to +85c 56-lead ch ip scale package, 62-kbyte, 5 v cp-56 aduc845bcp62-3 ?40c to +85c 56-lead ch ip scale package, 62-kbyte, 3 v cp-56 aduc845bcp8-5 ?40c to +85c 56-lead chip scale package, 8-kbyte, 5 v cp-56 aduc845bcp8-3 ?40c to +85c 56-lead chip scale package, 8-kbyte, 3 v cp-56 aduc845bsz62-5 t p 2 p t ?40c to +125c 52-lead plastic quad flatpack, lead free, 62-kbyte, 5 v s-52-2 aduc845bsz62-3 2 ?40c to +125c 52-lead plastic quad flatpack, lead free, 62-kbyte, 3 v s-52-2 aduc845bsz8-5 2 ?40c to +125c 52-lead plastic quad flatpack, lead free, 8-kbyte, 5 v s-52-2 aduc845bsz8-3 2 ?40c to +125c 52-lead plastic quad flatpack, lead free, 8-kbyte, 3 v s-52-2 aduc845bcpz62-5 2 ?40c to +85c 56-lead chip scale package, lead free, 62-kbyte, 5 v cp-56 aduc845bcpz62-3 2 ?40c to +85c 56-lead chip scale package, lead free, 62-kbyte, 3 v cp-56 aduc845bcpz8-5 2 ?40c to +85c 56-lead chip scale package, lead free, 8-kbyte, 5 v cp-56 aduc845bcpz8-3 2 ?40c to +85c 56-lead chip scale package, lead free, 8-kbyte, 3 v cp-56 aduc847bs62-5 ?40c to +125c 52-lead plasti c quad flatpack, 62-kbyte, 5 v s-52-2 aduc847bs62-3 ?40c to +125c 52-lead plasti c quad flatpack, 62-kbyte, 3 v s-52-2 aduc847bs32-5 ?40c to +125c 52-lead plasti c quad flatpack, 32-kbyte, 5 v s-52-2 aduc847bs32-3 ?40c to +125c 52-lead plasti c quad flatpack, 32-kbyte, 3 v s-52-2 aduc847bs8-5 ?40c to +125c 52-lead plasti c quad flatpack, 8-kbyte, 5 v s-52-2 aduc847bs8-3 ?40c to +125c 52-lead plasti c quad flatpack, 8-kbyte, 3 v s-52-2 aduc847bcp62-5 ?40c to +85c 56-lead ch ip scale package, 62-kbyte, 5 v cp-56 aduc847bcp62-3 ?40c to +85c 56-lead ch ip scale package, 62-kbyte, 3 v cp-56 aduc847bcp8-5 ?40c to +85c 56-lead chip scale package, 8-kbyte, 5 v cp-56 aduc847bcp8-3 ?40c to +85c 56-lead chip scale package, 8-kbyte, 3 v cp-56 aduc847bsz62-5 2 ?40c to +125c 52-lead plastic quad flatpack, lead free, 62-kbyte, 5 v s-52-2 aduc847bsz62-3 2 ?40c to +125c 52-lead plastic quad flatpack, lead free, 62-kbyte, 3 v s-52-2 aduc847bsz32-5 2 ?40c to +125c 52-lead plastic quad flatpack, lead free, 32-kbyte, 5 v s-52-2 aduc847bsz32-3 2 ?40c to +125c 52-lead plastic quad flatpack, lead free, 32-kbyte, 3 v s-52-2 aduc847bsz8-5 2 ?40c to +125c 52-lead plastic quad flatpack, lead free, 8-kbyte, 5 v s-52-2 aduc847bsz8-3 2 ?40c to +125c 52-lead plastic quad flatpack, lead free, 8-kbyte, 3 v s-52-2 aduc847bcpz62-5 2 ?40c to +85c 56-lead chip scale package, lead free, 62-kbyte, 5 v cp-56 aduc847bcpz62-3 2 ?40c to +85c 56-lead chip scale package, lead free, 62-kbyte, 3 v cp-56 aduc847bcpz8-5 2 ?40c to +85c 56-lead chip scale package, lead free, 8-kbyte, 5 v cp-56 aduc847bcpz8-3 2 ?40c to +85c 56-lead chip scale package, lead free, 8-kbyte, 3 v cp-56 aduc848bs62-5 ?40c to +125c 52-lead plasti c quad flatpack, 62-kbyte, 5 v s-52-2 aduc848bs62-3 ?40c to +125c 52-lead plasti c quad flatpack, 62-kbyte, 3 v s-52-2 aduc848bs32-5 ?40c to +125c 52-lead plasti c quad flatpack, 32-kbyte, 5 v s-52-2 aduc848bs32-3 ?40c to +125c 52-lead plasti c quad flatpack, 32-kbyte, 3 v s-52-2 aduc848bs8-5 ?40c to +125c 52-lead plasti c quad flatpack, 8-kbyte, 5 v s-52-2 aduc848bs8-3 ?40c to +125c 52-lead plasti c quad flatpack, 8-kbyte, 3 v s-52-2 aduc848bcp62-5 ?40c to +85c 56-lead ch ip scale package, 62-kbyte, 5 v cp-56 aduc848bcp62-3 ?40c to +85c 56-lead ch ip scale package, 62-kbyte, 3 v cp-56 aduc848bcp8-5 ?40c to +85c 56-lead chip scale package, 8-kbyte, 5 v cp-56 aduc848bcp8-3 ?40c to +85c 56-lead chip scale package, 8-kbyte, 3 v cp-56 aduc848bsz62-5 2 ?40c to +125c 52-lead plastic quad flatpack, lead free, 62-kbyte, 5 v s-52-2 aduc848bsz62-3 2 ?40c to +125c 52-lead plastic quad flatpack, lead free, 62-kbyte, 3 v s-52-2
aduc845/aduc847/aduc848 rev. b | page 106 of 108 aduc848bsz32-5 2 ?40c to +125c 52-lead plastic quad flatpack, lead free, 32-kbyte, 5 v s-52-2 aduc848bsz32-3 2 ?40c to +125c 52-lead plastic quad flatpack, lead free, 32-kbyte, 3 v s-52-2 aduc848bsz8-5 2 ?40c to +125c 52-lead plastic quad flatpack, lead free, 8-kbyte, 5 v s-52-2 aduc848bsz8-3 2 ?40c to +125c 52-lead plastic quad flatpack, lead free, 8-kbyte, 3 v s-52-2 aduc848bcpz62-5 2 ?40c to +85c 56-lead chip scale package, lead free, 62-kbyte, 5 v cp-56 aduc848bcpz62-3 2 ?40c to +85c 56-lead chip scale package, lead free, 62-kbyte, 3 v cp-56 aduc848bcpz8-5 2 ?40c to +85c 56-lead chip scale package, lead free, 8-kbyte, 5 v cp-56 aduc848bcpz8-3 2 ?40c to +85c 56-lead chip scale package, lead free, 8-kbyte, 3 v cp-56 eval-aduc845qs quickstart development system eval-aduc845qsp t p 3 p t quickstart-plus development system eval-aduc847qs quickstart development system eval-aduc847qsp 3 quickstart-plus development system t p 1 p t the -3 and -5 in the model column indicate the dv b dd b operating voltage. t p 2 p t z = pb-free part. t p 3 p t the quickstart plus system can only be ordered directly from accutron. it can be purchased from the website www.accutron.com.
aduc845/aduc847/aduc848 rev. b | page 107 of 108 notes
aduc845/aduc847/aduc848 rev. b | page 108 of 108 notes purchase of licensed i p 2 p c components of analog devices or one of its sublicensed associated companies conveys a license for the purchaser under the phi lips i p 2 p c patent rights to use these components in an i p 2 p c system, provided that the system conforms to the i p 2 p c standard specification as defined by philips. ? 2005 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d04741?0?2/05(b)

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